RTAX1000SL-1CGS624B vs RTAX1000SL-1CGS624V 比較
詳細並排比較 RTAX1000SL-1CGS624B 由 Microchip Technology 與 RTAX1000SL-1CGS624V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX1000SL-1CGS624B - Rad-Tolerant FPGA 1M Gates | Microchip
RTAX1000SL-1CGS624B ✓ 啟用中Microchip Technology
RTAX1000SL-1CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip
RTAX1000SL-1CGS624V ✓ 啟用中規格比較
| 參數 | RTAX1000SL-1CGS624B | RTAX1000SL-1CGS624V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Logic Density | 1,000,000 equivalent system gates | — |
| ASIC Gates | 125,000 additional ASIC gates | — |
| Configurable Logic Blocks (CLBs) | 12096 | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Series | RTAX1000SL | — |
| Speed Grade | -1 | -1 (standard) |
| Technology | Digital CMOS | — |
| Programming Technology | Anti-fuse (one-time programmable, live at power-up) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| 封裝 | 624-ball Ceramic CGA (CGS624) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Radiation Tolerance | Radiation-tolerant (space flight qualified) | Radiation-tolerant (space-flight qualified family) |
| Qualification | DLA SMD 5962-0422006QUA per MIL-PRF-38535 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| 供應電壓 | [DATA_NEEDED: core/IO supply voltage] | [DATA_NEEDED: core/IO supply voltage] |
| Maximum User I/O | [DATA_NEEDED: maximum user I/O count] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Architecture Base | Derived from Microsemi commercial Axcelerator family | — |
| System Gates | — | 1,000,000 (1.00E6) |
| Logic Cells / Logic Blocks | — | 12096 |
| Logic Family | — | Digital CMOS |
| Programmable Technology | — | Antifuse (one-time programmable) |
| Package Type | — | CGA-624 (ceramic column grid array) |
| 腳位數 | — | 624 |
| SEU Immunity | — | SEU-hardened registers; SEU rate < 10-10 errors/bit-day |
| Configuration | — | Live at power-up, single chip, no external boot PROM |
| Clocking | — | Segmentable clock resources |
| Routing Features | — | Chip-wide highway routing, carry logic |