SN75LVDS84ADGGR vs SN75LVDS84ADGG 比較
詳細並排比較 SN75LVDS84ADGGR 由 Texas Instruments 與 SN75LVDS84ADGG 由 Texas Instruments. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Texas Instruments
SN75LVDS84ADGGR - 21:3 FlatLink LVDS Transmitter 48-TSSOP | TI
SN75LVDS84ADGGR ✓ 啟用中Texas Instruments
SN75LVDS84ADGG - FlatLink 21:3 LVDS Transmitter | Texas Instruments
SN75LVDS84ADGG ✓ 啟用中規格比較
| 參數 | SN75LVDS84ADGGR | SN75LVDS84ADGG |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 類別 | Interface ICs | Interface ICs |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 功能 | LVDS FlatLink 21-bit transmitter (Serializer) | FlatLink Transmitter (LVDS Serializer) |
| Number of Drivers | 4 (3 data + 1 clock) | 4 (3 data + 1 clock) |
| 資料速率 | Up to 196 MBps (megabytes per second) | 196 MBps (MegaBytes per second) |
| 輸入電壓範圍 | 3 V to 3.6 V (LVTTL single-ended) | — |
| LVDS Output Swing | Typical 350 mV differential | — |
| Number of Input Channels | 21 LVTTL data + 1 clock | — |
| Number of Output Channels | 3 LVDS data pairs + 1 LVDS clock pair | — |
| Common-Mode Range | 0 V to 2.4 V | — |
| Propagation Delay | Typical 2.5 ns | [DATA_NEEDED: tPLH / tPHL values] |
| 工作溫度範圍 | 0 C to +70 C | — |
| Package Type | 48-TSSOP (DGG) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | 2 (1 year floor life) | [DATA_NEEDED: MSL rating] |
| RoHS 狀態 | Compliant | Compliant |
| Lead-Free | Yes | — |
| Family | FlatLink | — |
| AEC-Q100 Qualified | No (use SN65LVDS84AQDGG for automotive) | — |
| Parallel Inputs | — | 21 LVTTL data bits + 1 clock |
| Serial Outputs | — | 3 LVDS data pairs + 1 LVDS clock pair |
| 供應電壓 | — | 3.0 V to 3.6 V (3.3 V typical) |
| Supply Current (typical) | — | [DATA_NEEDED: ICC typical value] |
| LVDS Output Voltage Swing | — | [DATA_NEEDED: VOD differential swing] |
| LVTTL Input Voltage | — | [DATA_NEEDED: LVTTL input logic levels] |
| Clock Frequency Range | — | [DATA_NEEDED: parallel clock input range] |
| 工作溫度 | — | 0°C to +70°C (Commercial) |
| 封裝 | — | 48-pin TSSOP (DGG) |
| Data Channel Compression | — | 21:3 (21 bits serialized over 3 differential pairs) |