SN75LVDS84ADGGR vs SN75LVDS84ADGG Perbandingan
Perbandingan bersamaan detil SN75LVDS84ADGGR dari Texas Instruments dan SN75LVDS84ADGG dari Texas Instruments. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Texas Instruments
SN75LVDS84ADGGR - 21:3 FlatLink LVDS Transmitter 48-TSSOP | TI
SN75LVDS84ADGGR ✓ AktifTexas Instruments
SN75LVDS84ADGG - FlatLink 21:3 LVDS Transmitter | Texas Instruments
SN75LVDS84ADGG ✓ AktifPerbandingan Spesifikasi
| Parameter Umum | SN75LVDS84ADGGR | SN75LVDS84ADGG |
|---|---|---|
| Merek | Texas Instruments | Texas Instruments |
| Kategori | Interface ICs | Interface ICs |
| Status Lingkungan Hidup | Aktif | Aktif |
| Fungsi | LVDS FlatLink 21-bit transmitter (Serializer) | FlatLink Transmitter (LVDS Serializer) |
| Number of Drivers | 4 (3 data + 1 clock) | 4 (3 data + 1 clock) |
| Laju Data | Up to 196 MBps (megabytes per second) | 196 MBps (MegaBytes per second) |
| Rentang Tegangan Masukan | 3 V to 3.6 V (LVTTL single-ended) | — |
| LVDS Output Swing | Typical 350 mV differential | — |
| Number of Input Channels | 21 LVTTL data + 1 clock | — |
| Number of Output Channels | 3 LVDS data pairs + 1 LVDS clock pair | — |
| Common-Mode Range | 0 V to 2.4 V | — |
| Propagation Delay | Typical 2.5 ns | [DATA_NEEDED: tPLH / tPHL values] |
| Rentang Suhu Kerja | 0 C to +70 C | — |
| Package Type | 48-TSSOP (DGG) | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Level MSL | 2 (1 year floor life) | [DATA_NEEDED: MSL rating] |
| Status RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Family | FlatLink | — |
| AEC-Q100 Qualified | No (use SN65LVDS84AQDGG for automotive) | — |
| Parallel Inputs | — | 21 LVTTL data bits + 1 clock |
| Serial Outputs | — | 3 LVDS data pairs + 1 LVDS clock pair |
| Tegangan Pemuat | — | 3.0 V to 3.6 V (3.3 V typical) |
| Supply Current (typical) | — | [DATA_NEEDED: ICC typical value] |
| LVDS Output Voltage Swing | — | [DATA_NEEDED: VOD differential swing] |
| LVTTL Input Voltage | — | [DATA_NEEDED: LVTTL input logic levels] |
| Clock Frequency Range | — | [DATA_NEEDED: parallel clock input range] |
| Suhu Kerja | — | 0°C to +70°C (Commercial) |
| Paket | — | 48-pin TSSOP (DGG) |
| Data Channel Compression | — | 21:3 (21 bits serialized over 3 differential pairs) |