ADC081000CIYB - 8-Bit 1 GSPS ADC, 128-HLQFP | Texas Instruments
MPN： ADC081000CIYB ✗ 停產ADC081000CIYB 概覽
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time analog voltage or current into a discrete digital code. The ADC081000 sits in the high-speed pipeline / folding-and-interpolating converter family, which combines pipelined sub-ranges with analog interpolation stages. This hierarchy positions it within power-management-adjacent data-conversion ICs, frequently co-designed with high-performance DACs in transmit/receive signal chains, oscilloscopes, and digital sampling oscilloscope front ends.
Key features of the ADC081000 include 7.0 effective bits at 500 MHz input (typical), a 1.4 GHz full-power analog input bandwidth, low latency suitable for real-time systems, and selectable LVDS or DDR CMOS output formats that ease interface to Xilinx and Altera FPGAs. The internal reference eliminates external reference noise injection, while the differential PECL/LVDS-compatible clock input supports sub-picosecond jitter generation when fed from a clean source. Power dissipation is approximately 1.4 W at 1 GSPS from a single 1.9 V analog supply plus 1.9 V digital supply.
The folding/interpolating topology partitions the 8-bit conversion into coarse and fine sub-conversions, then uses analog interpolation to resolve the fine bits. This architecture avoids the latency typical of long pipelined stages while still achieving multi-hundred-MHz sample rates, making the ADC081000 well suited to time-domain instrumentation. The exposed-pad HLQFP provides a thermal resistance around 18 C/W junction-to-case, supporting 1 GSPS sustained operation with proper PCB thermal relief.
Typical applications include digital oscilloscopes, spectrum analyzer IF digitizers, radar IF sampling, high-end test-and-measurement equipment, and digital pre-distortion feedback loops for wireless infrastructure. Its 1 GSPS rate aligns naturally with 500 MHz analog front ends needed in pulsed-RF instrumentation and optical sampling front-ends.
When designing with this part, place the exposed-pad copper pour on at least four inner PCB layers stitched by a 4 x 4 thermal via array to keep junction temperature below 110 C. Use differential clock routing with 100 ohm controlled impedance and length-match data lanes within ±20 ps to avoid inter-symbol jitter; a stable, low-jitter clock source such as TI's LMK04800 clock conditioner is recommended.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 ADC081000CIYB — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADC081000CIYB （相同外形與佔位） — 差異在於 Architecture, Package, Operating Temperature Range, Resolution, Number of Input Channels.
ADC081000CIYB/NOPB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC083000CIYB
✅ 直接替換📋 參考替代品（不在目錄中）
ADC081000CIYB
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →ADC081000CIYB 最大額定值與電氣特性
| 解析度 | 8 bit |
| Sampling Rate (Max) | 1 GSPS |
| Number of Channels | 1 |
| Architecture | Folding and Interpolating with Internal Sample-and-Hold |
| Analog Input Bandwidth | 1.4 GHz (full power) |
| ENOB at 500 MHz Input | 7.0 effective bits (typical) |
| Analog Supply Voltage | 1.9 V |
| Digital Supply Voltage | 1.9 V |
| Power Dissipation at 1 GSPS | 1.4 W (typical) |
| Reference Type | Internal |
| Output Format | LVDS or DDR CMOS (selectable) |
| Clock Input | Differential PECL/LVDS compatible |
| 工作溫度範圍 | -40 C to +85 C |
| 封裝 | 128-HLQFP (20 mm x 20 mm) with Exposed Pad |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant (NOPB suffix) |
ADC081000CIYB 腳位配置
| 腳位 1 | AGND — Analog ground |
| 腳位 2 | VIN+ — Differential analog input (positive) |
| 腳位 3 | VIN- — Differential analog input (negative) |
| 腳位 4 | AGND — Analog ground |
| 腳位 5 | VA1.9 — 1.9 V analog supply |
| 腳位 6 | VBY1.9 — 1.9 V reference supply |
| 腳位 7 | AGND — Analog ground |
| 腳位 8 | CLK+ — Differential clock input (positive) |
| 腳位 9 | CLK- — Differential clock input (negative) |
| 腳位 10 | AGND — Analog ground |
| 腳位 11 | PD — Power down (active high) |
| 腳位 12 | DFS — Data format select (LVDS / DDR-CMOS) |
| 腳位 13 | FSR — Full-scale range select |
| 腳位 14 | CAL — Calibration mode select |
| 腳位 15 | OGND — Output ground |
| 腳位 16 | VD1.9 — 1.9 V digital supply |
| 腳位 17 | OGND — Output ground |
| 腳位 18 | D0+ — LVDS data output bit 0 (positive) |
| 腳位 19 | D0- — LVDS data output bit 0 (negative) |
| 腳位 20 | D1+ — LVDS data output bit 1 (positive) |
| 腳位 21 | D1- — LVDS data output bit 1 (negative) |
| 腳位 22 | OGND — Output ground |
| 腳位 23 | D2+ — LVDS data output bit 2 (positive) |
| 腳位 24 | D2- — LVDS data output bit 2 (negative) |
| 腳位 25 | D3+ — LVDS data output bit 3 (positive) |
| 腳位 26 | D3- — LVDS data output bit 3 (negative) |
| 腳位 27 | OGND — Output ground |
| 腳位 28 | D4+ — LVDS data output bit 4 (positive) |
| 腳位 29 | D4- — LVDS data output bit 4 (negative) |
| 腳位 30 | D5+ — LVDS data output bit 5 (positive) |
| 腳位 31 | D5- — LVDS data output bit 5 (negative) |
| 腳位 32 | OGND — Output ground |
| 腳位 33 | D6+ — LVDS data output bit 6 (positive) |
| 腳位 34 | D6- — LVDS data output bit 6 (negative) |
| 腳位 35 | D7+ — LVDS data output bit 7 (positive) |
| 腳位 36 | D7- — LVDS data output bit 7 (negative) |
| 腳位 37 | OGND — Output ground |
| 腳位 38 | OR+ — LVDS out-of-range (positive) |
| 腳位 39 | OR- — LVDS out-of-range (negative) |
| 腳位 40 | OGND — Output ground |
| 腳位 41 | DGND — Digital ground |
| 腳位 42 | DGND — Digital ground |
| 腳位 43 | DGND — Digital ground |
| 腳位 44 | DGND — Digital ground |
| 腳位 45 | DGND — Digital ground |
| 腳位 46 | DGND — Digital ground |
| 腳位 47 | DGND — Digital ground |
| 腳位 48 | DGND — Digital ground |
| 腳位 49 | DGND — Digital ground |
| 腳位 50 | DGND — Digital ground |
| 腳位 51 | AGND — Analog ground |
| 腳位 52 | AGND — Analog ground |
| 腳位 53 | AGND — Analog ground |
| 腳位 54 | AGND — Analog ground |
| 腳位 55 | AGND — Analog ground |
| 腳位 56 | AGND — Analog ground |
| 腳位 57 | AGND — Analog ground |
| 腳位 58 | AGND — Analog ground |
| 腳位 59 | AGND — Analog ground |
| 腳位 60 | AGND — Analog ground |
| 腳位 61 | AGND — Analog ground |
| 腳位 62 | AGND — Analog ground |
| 腳位 63 | VA1.9 — 1.9 V analog supply |
| 腳位 64 | VA1.9 — 1.9 V analog supply |
| 腳位 65 | VA1.9 — 1.9 V analog supply |
| 腳位 66 | VA1.9 — 1.9 V analog supply |
| 腳位 67 | VA1.9 — 1.9 V analog supply |
| 腳位 68 | VA1.9 — 1.9 V analog supply |
| 腳位 69 | VA1.9 — 1.9 V analog supply |
| 腳位 70 | VA1.9 — 1.9 V analog supply |
| 腳位 71 | VA1.9 — 1.9 V analog supply |
| 腳位 72 | VA1.9 — 1.9 V analog supply |
| 腳位 73 | VBY1.9 — 1.9 V reference supply |
| 腳位 74 | VBY1.9 — 1.9 V reference supply |
| 腳位 75 | AGND — Analog ground |
| 腳位 76 | TEST — Factory test pin (do not connect) |
| 腳位 77 | TEST — Factory test pin (do not connect) |
| 腳位 78 | TEST — Factory test pin (do not connect) |
| 腳位 79 | TEST — Factory test pin (do not connect) |
| 腳位 80 | TEST — Factory test pin (do not connect) |
| 腳位 81 | VD1.9 — 1.9 V digital supply |
| 腳位 82 | VD1.9 — 1.9 V digital supply |
| 腳位 83 | VD1.9 — 1.9 V digital supply |
| 腳位 84 | VD1.9 — 1.9 V digital supply |
| 腳位 85 | VD1.9 — 1.9 V digital supply |
| 腳位 86 | VD1.9 — 1.9 V digital supply |
| 腳位 87 | VD1.9 — 1.9 V digital supply |
| 腳位 88 | VD1.9 — 1.9 V digital supply |
| 腳位 89 | VD1.9 — 1.9 V digital supply |
| 腳位 90 | VD1.9 — 1.9 V digital supply |
| 腳位 91 | OGND — Output ground |
| 腳位 92 | OGND — Output ground |
| 腳位 93 | OGND — Output ground |
| 腳位 94 | OGND — Output ground |
| 腳位 95 | OGND — Output ground |
| 腳位 96 | OGND — Output ground |
| 腳位 97 | OGND — Output ground |
| 腳位 98 | OGND — Output ground |
| 腳位 99 | OGND — Output ground |
| 腳位 100 | OGND — Output ground |
| 腳位 101 | NC — Not connected (per datasheet) |
| 腳位 102 | NC — Not connected (per datasheet) |
| 腳位 103 | NC — Not connected (per datasheet) |
| 腳位 104 | NC — Not connected (per datasheet) |
| 腳位 105 | NC — Not connected (per datasheet) |
| 腳位 106 | NC — Not connected (per datasheet) |
| 腳位 107 | NC — Not connected (per datasheet) |
| 腳位 108 | NC — Not connected (per datasheet) |
| 腳位 109 | DNC — Reserved, leave unconnected |
| 腳位 110 | DNC — Reserved, leave unconnected |
| 腳位 111 | DNC — Reserved, leave unconnected |
| 腳位 112 | DNC — Reserved, leave unconnected |
| 腳位 113 | DNC — Reserved, leave unconnected |
| 腳位 114 | DNC — Reserved, leave unconnected |
| 腳位 115 | DNC — Reserved, leave unconnected |
| 腳位 116 | DNC — Reserved, leave unconnected |
| 腳位 117 | DNC — Reserved, leave unconnected |
| 腳位 118 | DNC — Reserved, leave unconnected |
| 腳位 119 | DNC — Reserved, leave unconnected |
| 腳位 120 | DNC — Reserved, leave unconnected |
| 腳位 121 | DGND — Digital ground |
| 腳位 122 | DGND — Digital ground |
| 腳位 123 | DGND — Digital ground |
| 腳位 124 | DGND — Digital ground |
| 腳位 125 | DGND — Digital ground |
| 腳位 126 | DGND — Digital ground |
| 腳位 127 | DGND — Digital ground |
| 腳位 128 | VREF — Reference voltage (internal bypass cap pin) |
典型應用
ADC081000CIYB 適用於 6 應用s: Digital Oscilloscope Front-End, Spectrum Analyzer IF Digitizer, Radar IF Sampling, Test & Measurement Instrumentation, Digital Pre-Distortion Feedback Loops, Optical Sampling & LIDAR Receiver.
Digital Oscilloscope Front-End
The ADC081000's 1 GSPS sample rate and 1.4 GHz analog input bandwidth place it as a 1-channel or 2-channel interleaved front end in digital storage oscilloscopes targeting 200-500 MHz bandwidth. With 7.0 effective bits at 500 MHz input and LVDS/DDR-CMOS selectable outputs, the part drives Xilinx Kintex or Altera Cyclone FPGAs at full 1 GSPS while maintaining sub-picosecond aperture jitter. In a typical DSO design the ADC081000 digitizes the post-attenuator/amplifier signal, with the FPGA performing trigger, decimation, and display processing.
推薦
Spectrum Analyzer IF Digitizer
At a 1 GSPS sample rate the ADC081000 digitizes intermediate-frequency signals in the 0-500 MHz band for digital-IF spectrum analyzers. The folding/interpolating architecture delivers low aperture delay under 2 ns, enabling real-time FFT processing without pipeline-latency compensation. Designers pair the converter with an FPGA-based FFT accelerator running at the LVDS data rate (DDR-CMOS at 250 MHz x 8 bits = 2 Gbps LVDS aggregate), enabling 100 kHz resolution bandwidth FFTs without aliasing from the converter.
推薦
Radar IF Sampling
Pulsed-radar receivers down-convert RF to a 100-400 MHz IF that the ADC081000 digitizes at 1 GSPS, capturing the full pulse envelope and supporting moving-target indication. The 7.0 ENOB dynamic range is adequate for primary radar at moderate PRF; the internal sample-and-hold and 1.4 GHz input bandwidth ease analog front-end design. The exposed-pad HLQFP provides sufficient thermal margin for continuous 1 GSPS operation in airborne radar pods with proper PCB thermal design.
推薦
Test & Measurement Instrumentation
Automated test equipment (ATE) and bench-top instruments leverage the ADC081000's 1 GSPS capability for capturing repetitive waveforms with picosecond-class timing resolution. The differential clock input accepts a low-jitter source such as an LMK04800, and the selectable DDR-CMOS or LVDS output directly drives FPGAs for waveform averaging and statistical analysis. The 1.9 V dual-supply design requires careful PCB layout with separate analog/digital ground planes stitched at the exposed pad.
推薦
Digital Pre-Distortion Feedback Loops
Wideband wireless base-station transmitters use ADC081000-class converters in the DPD (digital pre-distortion) feedback path to sample the PA output and correct AM-AM/AM-PM distortion. Sampling at 1 GSPS with a 200-400 MHz IF accommodates LTE/5G NR signal bandwidths up to 100 MHz plus observation bandwidth. The selectable LVDS output easily fits the FPGA-based DPD engine running at hundreds of MSPS of complex signal processing.
推薦
Optical Sampling & LIDAR Receiver
Pulsed optical receivers (LIDAR, time-of-flight sensors) use the ADC081000 to digitize echo returns sampled at 1 GSPS, achieving 1 ns time-bin resolution for short-range depth mapping. The 1.4 GHz analog input bandwidth matches the fast-edge transimpedance amplifier signal chain, while the folding/interpolating architecture minimizes pipeline latency. With two ADCs interleaved on a common clock, the effective sample rate can be doubled to 2 GSPS without redesigning the analog front end.
推薦
推薦產品摘要
工程參考資料，適用於 ADC081000CIYB — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADC081000CIYB/NOPB | ADC083000CIYB | ADC081000CIYB |
|---|---|---|---|---|
| Package | 128-HLQFP (20x20 mm, exposed pad) | 128-HLQFP (20x20 mm, exposed pad) - same | 128-HLQFP (20x20 mm, exposed pad) - same | 128-HLQFP (20x20 mm, exposed pad) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit |
| Max Sample Rate | 1 GSPS | 1 GSPS | 3 GSPS | 1 GSPS |
| Input Bandwidth | 1.4 GHz | 1.4 GHz | 2.7 GHz | 1.4 GHz |
| ENOB at 500 MHz | 7.0 bits (typical) | 7.0 bits | 6.8 bits | 7.0 bits |
| Supply Voltage | 1.9 V analog + 1.9 V digital | 1.9 V + 1.9 V | 1.9 V + 1.9 V | 1.9 V + 1.9 V |
| Power Dissipation | 1.4 W at 1 GSPS | 1.4 W at 1 GSPS | 3.5 W at 3 GSPS | 1.4 W at 1 GSPS |
| Output Format | LVDS or DDR CMOS | LVDS or DDR CMOS | LVDS or DDR CMOS | LVDS or DDR CMOS |
| RoHS Status | Leaded variant | RoHS compliant (lead-free) | RoHS compliant | Leaded variant |
主要差異化特點
- Pin-compatible upgrade path to 3 GSPS (對比ADC083000CIYB)
- Lower power dissipation than 3 GSPS variant (對比ADC083000CIYB)
- RoHS-compliant variant available with identical die (對比ADC081000CIYB/NOPB)
- Internal reference eliminates external noise injection (對比External-reference ADCs)
設計說明
Estimated: At 1 GSPS continuous operation, the ADC081000 dissipates approximately 1.4 W. With the 128-HLQFP exposed-pad package having a theta_JC of approximately 1.8 C/W and theta_JA around 18 C/W on a 4-layer JEDEC board, the junction-to-ambient temperature rise is approximately 25 C. Above 70 C ambient, additional copper area or active airflow is recommended. The exposed pad must be soldered directly to a continuous copper pour on the top layer, with a 4 x 4 thermal-via array stitching to all four inner-layer ground planes to keep the junction below 110 C.
Use a 4-layer (or 6-layer) PCB with separate analog and digital/digital-IO ground planes that join only at the ADC's exposed pad. Place 0.1 µF X7R bypass capacitors within 5 mm of every VA1.9, VD1.9, and VBY1.9 pin pair, plus 10 µF bulk caps on each supply. Route the differential analog input (VIN+/VIN-) and the differential clock (CLK+/CLK-) on 100 ohm controlled-impedance traces with length matching within ±0.5 mm. Keep all LVDS data pairs length-matched within ±0.25 mm and skew-matched across lanes to avoid bit-skew.
Estimated: Source the differential clock from a low-jitter generator (e.g., TI LMK04800 or LMK03806) with sub-200 fs RMS jitter to keep aperture-induced SNR degradation below 0.5 dB. Terminate the clock pair at the ADC's pins with 100 ohm differential, not at the source. Use an external clock-jitter budget under 0.5 ps RMS to maintain the rated 7.0 ENOB at 500 MHz input. AC-couple the clock if the source is biased at a non-standard common-mode voltage.
Do not exceed the absolute maximum 2.2 V supply on any VA1.9, VD1.9, or VBY1.9 pin; over-voltage damages the LVDS drivers. Always enable the analog supply first, then the digital supply, with a controlled 1 ms ramp to prevent latch-up. The TEST pins (76-80) are factory-test points and must be left floating - they are NOT reserved for customer use. Failure to solder the exposed die-attach pad during assembly causes thermal runaway at 1 GSPS continuous operation.
合規資訊
The bare ADC081000CIYB uses a leaded finish and is NOT RoHS compliant. The /NOPB variant (ADC081000CIYB/NOPB) is RoHS compliant with matte-tin lead-free finish. Reach compliance and conflict-minerals statement are per TI Product Ecology documents. AEC-Q100 qualification is not applicable - this part is rated industrial (-40 C to +85 C), not automotive.
