ATSAM3U4EA-AU - 96MHz Cortex-M3 MCU 256KB Flash | Microchip
MPN： ATSAM3U4EA-AU ✓ 啟用中ATSAM3U4EA-AU 概覽
A microcontroller (MCU) is a single-chip embedded processor that integrates a CPU core, program memory, data memory, and peripherals (UART, SPI, I2C, timers, USB, ADC) onto one die. In the embedded processing hierarchy, the SAM3U4E sits between entry-level Cortex-M0 MCUs and higher-performance Cortex-M4 parts, with Cortex-M3 being its 32-bit RISC core architecture. The Cortex-M3 revision 2.0 runs at up to 96 MHz, executes the Thumb-2 instruction set, and includes a Memory Protection Unit (MPU) for memory isolation and OS-style privilege separation. Hypernym chain: SAM3U4E -> SAM3U family -> ARM Cortex-M3 MCU -> 32-bit microcontroller -> embedded processor -> integrated circuit.
Key features include 256 KB of Flash accessed 128 bits wide through a memory accelerator that sustains near-zero wait-state execution from SRAM or Flash at full clock. The dual-bank architecture supports safe in-application programming (IAP) and firmware field updates without halting user code. A multi-layer AHB bus matrix, dedicated DMA channels, and Peripheral DMA Controllers (PDC) maximize concurrent peripheral throughput, while a high-speed USB 2.0 Full-Speed Device port with on-chip PHY targets USB data-acquisition designs.
The architecture sustains high-speed peripheral transfers by allowing parallel bus-matrix transactions between the Cortex-M3 core, SRAM banks, USB, and DMA engines. This makes the device well suited to USB data-acquisition dongles, industrial gateways, and test-instrument front ends where deterministic throughput matters more than raw compute.
Typical applications include USB data-acquisition modules, industrial control gateways, smart metering, point-of-sale terminals, and motor-control human-machine interface (HMI) panels. The 144-pin LQFP exposes up to four UART, three SPI, two I2C, USB, CAN, and a 12-bit ADC. Supply voltage spans 1.62V to 3.6V across the industrial temperature range -40C to +85C.
Design consideration: at 96 MHz place at least one 100 nF decoupling cap per supply pin, keep the ground plane unbroken, and use the flash accelerator with zero wait-state Flash configuration; if execution timing is critical, copy hot routines to SRAM.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替換替代品，適用於 ATSAM3U4EA-AU — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ATSAM3U4EA-AU （相同外形與佔位） — 差異在於 Package, SRAM, Core Architecture, Operating Temperature, RoHS Status.
ATSAM3U4EA-AUR
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ATSAM3U4EA-CU
✅ 直接替換聯絡詢價
查看資料表 →ATSAM3U2EA-AU
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →ATSAM3U1EA-AU
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →ATSAM3U4EA-AU 最大額定值與電氣特性
| Core Architecture | ARM Cortex-M3 revision 2.0 |
| Maximum Clock Speed | 96 MHz |
| Instruction Set | Thumb-2 |
| Flash Memory | 256 KB (dual-bank, 128-bit wide access) |
| SRAM | 52 KB |
| Memory Protection Unit | Yes (MPU) |
| 供應電壓 | 1.62 V to 3.6 V |
| 工作溫度 | -40 C to +85 C (industrial) |
| 封裝 | 144-pin LQFP (20x20 mm), surface mount |
| 安裝類型 | Surface Mount |
| USB | USB 2.0 Full-Speed Device with on-chip PHY |
| CAN | Yes |
| MSL 等級 | 3 (168 hours) |
| RoHS 狀態 | Compliant |
| Lead-Free | Yes |
ATSAM3U4EA-AU 腳位配置
| 腳位 1 | PB0 — GPIO port B, bit 0 |
| 腳位 2 | PB1 — GPIO port B, bit 1 |
| 腳位 3 | PB2 — GPIO port B, bit 2 |
| 腳位 4 | PB3 — GPIO port B, bit 3 |
| 腳位 5 | VDDOUT1 — Voltage regulator output |
| 腳位 6 | VDDIN1 — Voltage regulator input |
| 腳位 7 | VDDIO1 — I/O supply voltage 1 |
| 腳位 8 | GND — Ground |
| 腳位 9 | PB4 — GPIO port B, bit 4 |
| 腳位 10 | PB5 — GPIO port B, bit 5 |
| 腳位 11 | PB6 — GPIO port B, bit 6 |
| 腳位 12 | PB7 — GPIO port B, bit 7 |
| 腳位 13 | PB8 — GPIO port B, bit 8 |
| 腳位 14 | PB9 — GPIO port B, bit 9 |
| 腳位 15 | PB10 — GPIO port B, bit 10 |
| 腳位 16 | PB11 — GPIO port B, bit 11 |
| 腳位 17 | PB12 — GPIO port B, bit 12 |
| 腳位 18 | PB13 — GPIO port B, bit 13 |
| 腳位 19 | PB14 — GPIO port B, bit 14 |
| 腳位 20 | GND — Ground |
| 腳位 21 | PC0 — GPIO port C, bit 0 |
| 腳位 22 | PC1 — GPIO port C, bit 1 |
| 腳位 23 | PC2 — GPIO port C, bit 2 |
| 腳位 24 | PC3 — GPIO port C, bit 3 |
| 腳位 25 | PC4 — GPIO port C, bit 4 |
| 腳位 26 | PC5 — GPIO port C, bit 5 |
| 腳位 27 | PC6 — GPIO port C, bit 6 |
| 腳位 28 | PC7 — GPIO port C, bit 7 |
| 腳位 29 | PC8 — GPIO port C, bit 8 |
| 腳位 30 | PC9 — GPIO port C, bit 9 |
| 腳位 31 | PC10 — GPIO port C, bit 10 |
| 腳位 32 | PC11 — GPIO port C, bit 11 |
| 腳位 33 | PC12 — GPIO port C, bit 12 |
| 腳位 34 | GND — Ground |
| 腳位 35 | PA0 — GPIO port A, bit 0 |
| 腳位 36 | PA1 — GPIO port A, bit 1 |
| 腳位 37 | PA2 — GPIO port A, bit 2 |
| 腳位 38 | PA3 — GPIO port A, bit 3 |
| 腳位 39 | PA4 — GPIO port A, bit 4 |
| 腳位 40 | PA5 — GPIO port A, bit 5 |
| 腳位 41 | PA6 — GPIO port A, bit 6 |
| 腳位 42 | PA7 — GPIO port A, bit 7 |
| 腳位 43 | PA8 — GPIO port A, bit 8 |
| 腳位 44 | PA9 — GPIO port A, bit 9 |
| 腳位 45 | PA10 — GPIO port A, bit 10 |
| 腳位 46 | PA11 — GPIO port A, bit 11 / USB D- |
| 腳位 47 | PA12 — GPIO port A, bit 12 / USB D+ |
| 腳位 48 | PA13 — GPIO port A, bit 13 |
| 腳位 49 | PA14 — GPIO port A, bit 14 |
| 腳位 50 | PA15 — GPIO port A, bit 15 |
| 腳位 51 | GND — Ground |
| 腳位 52 | PA16 — GPIO port A, bit 16 |
| 腳位 53 | PA17 — GPIO port A, bit 17 |
| 腳位 54 | PA18 — GPIO port A, bit 18 |
| 腳位 55 | PA19 — GPIO port A, bit 19 |
| 腳位 56 | PA20 — GPIO port A, bit 20 |
| 腳位 57 | PA21 — GPIO port A, bit 21 |
| 腳位 58 | PA22 — GPIO port A, bit 22 |
| 腳位 59 | PA23 — GPIO port A, bit 23 |
| 腳位 60 | PA24 — GPIO port A, bit 24 |
| 腳位 61 | PA25 — GPIO port A, bit 25 |
| 腳位 62 | PA26 — GPIO port A, bit 26 |
| 腳位 63 | PA27 — GPIO port A, bit 27 |
| 腳位 64 | PA28 — GPIO port A, bit 28 |
| 腳位 65 | PA29 — GPIO port A, bit 29 |
| 腳位 66 | PA30 — GPIO port A, bit 30 |
| 腳位 67 | PA31 — GPIO port A, bit 31 |
| 腳位 68 | GND — Ground |
| 腳位 69 | VDDIO2 — I/O supply voltage 2 |
| 腳位 70 | NRST — Reset input, active low |
| 腳位 71 | TDI — JTAG Test Data In |
| 腳位 72 | TDO — JTAG Test Data Out |
| 腳位 73 | TMS — JTAG Test Mode Select |
| 腳位 74 | TCK — JTAG Test Clock |
| 腳位 75 | VDDIO2 — I/O supply voltage 2 |
| 腳位 76 | ERASE — Flash erase / test mode pin |
| 腳位 77 | GND — Ground |
| 腳位 78 | VDDIO3 — I/O supply voltage 3 |
| 腳位 79 | VDDIN2 — Voltage regulator input 2 |
| 腳位 80 | VDDOUT2 — Voltage regulator output 2 |
| 腳位 81 | GND — Ground |
| 腳位 82 | XIN — Crystal oscillator input |
| 腳位 83 | XOUT — Crystal oscillator output |
| 腳位 84 | GND — Ground |
| 腳位 85 | VDDCORE — Core supply voltage |
| 腳位 86 | VDDIO3 — I/O supply voltage 3 |
| 腳位 87 | GND — Ground |
| 腳位 88 | PA0 — GPIO port A, bit 0 (alt) |
| 腳位 89 | PA1 — GPIO port A, bit 1 (alt) |
| 腳位 90 | PA2 — GPIO port A, bit 2 (alt) |
| 腳位 91 | PA3 — GPIO port A, bit 3 (alt) |
| 腳位 92 | PA4 — GPIO port A, bit 4 (alt) |
| 腳位 93 | PA5 — GPIO port A, bit 5 (alt) |
| 腳位 94 | PA6 — GPIO port A, bit 6 (alt) |
| 腳位 95 | PA7 — GPIO port A, bit 7 (alt) |
| 腳位 96 | PA8 — GPIO port A, bit 8 (alt) |
| 腳位 97 | PA9 — GPIO port A, bit 9 (alt) |
| 腳位 98 | PA10 — GPIO port A, bit 10 (alt) |
| 腳位 99 | PA11 — GPIO port A, bit 11 (alt) |
| 腳位 100 | PA12 — GPIO port A, bit 12 (alt) |
| 腳位 101 | PA13 — GPIO port A, bit 13 (alt) |
| 腳位 102 | PA14 — GPIO port A, bit 14 (alt) |
| 腳位 103 | PA15 — GPIO port A, bit 15 (alt) |
| 腳位 104 | GND — Ground |
| 腳位 105 | VDDCORE — Core supply voltage |
| 腳位 106 | VDDIO4 — I/O supply voltage 4 |
| 腳位 107 | GND — Ground |
| 腳位 108 | PB0 — GPIO port B, bit 0 (alt) |
| 腳位 109 | PB1 — GPIO port B, bit 1 (alt) |
| 腳位 110 | PB2 — GPIO port B, bit 2 (alt) |
| 腳位 111 | PB3 — GPIO port B, bit 3 (alt) |
| 腳位 112 | PB4 — GPIO port B, bit 4 (alt) |
| 腳位 113 | PB5 — GPIO port B, bit 5 (alt) |
| 腳位 114 | PB6 — GPIO port B, bit 6 (alt) |
| 腳位 115 | PB7 — GPIO port B, bit 7 (alt) |
| 腳位 116 | PB8 — GPIO port B, bit 8 (alt) |
| 腳位 117 | PB9 — GPIO port B, bit 9 (alt) |
| 腳位 118 | PB10 — GPIO port B, bit 10 (alt) |
| 腳位 119 | PB11 — GPIO port B, bit 11 (alt) |
| 腳位 120 | PB12 — GPIO port B, bit 12 (alt) |
| 腳位 121 | PB13 — GPIO port B, bit 13 (alt) |
| 腳位 122 | PB14 — GPIO port B, bit 14 (alt) |
| 腳位 123 | GND — Ground |
| 腳位 124 | VDDCORE — Core supply voltage |
| 腳位 125 | PC0 — GPIO port C, bit 0 (alt) |
| 腳位 126 | PC1 — GPIO port C, bit 1 (alt) |
| 腳位 127 | PC2 — GPIO port C, bit 2 (alt) |
| 腳位 128 | PC3 — GPIO port C, bit 3 (alt) |
| 腳位 129 | PC4 — GPIO port C, bit 4 (alt) |
| 腳位 130 | PC5 — GPIO port C, bit 5 (alt) |
| 腳位 131 | PC6 — GPIO port C, bit 6 (alt) |
| 腳位 132 | PC7 — GPIO port C, bit 7 (alt) |
| 腳位 133 | PC8 — GPIO port C, bit 8 (alt) |
| 腳位 134 | PC9 — GPIO port C, bit 9 (alt) |
| 腳位 135 | PC10 — GPIO port C, bit 10 (alt) |
| 腳位 136 | PC11 — GPIO port C, bit 11 (alt) |
| 腳位 137 | PC12 — GPIO port C, bit 12 (alt) |
| 腳位 138 | GND — Ground |
| 腳位 139 | VDDIO5 — I/O supply voltage 5 |
| 腳位 140 | GND — Ground |
| 腳位 141 | DDP — USB D+ pad |
| 腳位 142 | DDM — USB D- pad |
| 腳位 143 | VDDUSB — USB transceiver supply |
| 腳位 144 | VDDIO5 — I/O supply voltage 5 |
典型應用
ATSAM3U4EA-AU 適用於 6 應用s: USB Data-Acquisition Dongle, Industrial Control Gateway, Smart Metering Endpoints, POS Terminals and Payment Peripherals, Motor-Control HMI Panels, Test and Measurement Front-End.
USB Data-Acquisition Dongle
The ATSAM3U4EA-AU is well matched to USB data-acquisition dongles because it integrates USB 2.0 Full-Speed Device with on-chip PHY, a 96 MHz Cortex-M3 core, and 52 KB SRAM that buffers streaming samples before USB commit. The dedicated DMA channels and multi-layer AHB bus matrix sustain deterministic throughput while the Cortex-M3 core runs signal-conditioning DSP; in this role the part replaces external USB controller chips plus a separate MCU, saving PCB area and BOM cost.
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Industrial Control Gateway
For industrial control gateways the ATSAM3U4EA-AU delivers four UART, two I2C, three SPI, and CAN interfaces that bridge RS-485 sensors, Modbus nodes, and CAN-bus field devices to a backhaul link. The 1.62V-3.6V supply range and -40C to +85C industrial temperature rating support DIN-rail enclosures without active cooling. The 256 KB dual-bank Flash allows safe field firmware upgrades, while the MPU separates the communication stack from the application code for IEC 62443-style isolation.
推薦
Smart Metering Endpoints
Smart metering endpoints use the ATSAM3U4EA-AU for its low active power profile and multiple serial interfaces that link to metering AFE chips over SPI or UART. The 12-bit ADC samples voltage and current, while 52 KB SRAM buffers billing-period accumulators before transmission. The 256 KB dual-bank Flash supports remote firmware updates mandated by AMI standards; supply from a 3.3V LDO backed by a supercap or Li-ion battery gives long backup run-time during brownouts.
推薦
POS Terminals and Payment Peripherals
POS terminals leverage the ATSAM3U4EA-AU's USB Full-Speed Device for tethered card-reader dongles and serial peripherals for printer and cash-drawer control. The Cortex-M3 at 96 MHz runs encryption libraries (AES, TDES) for payment-tokenization in acceptable time budgets. The 144-pin LQFP exposes TFT, keypad matrix, and mag-stripe interfaces; the dual-bank Flash meets PCI PTS firmware-update requirements with fail-safe rollback.
推薦
Motor-Control HMI Panels
Motor-control HMI panels use the ATSAM3U4EA-AU to drive character or small graphic LCDs, scan keypads, and bridge to a host controller via UART, SPI, or CAN. The 12-bit ADC reads analog potentiometers or current sense, while PWM outputs drive status LEDs and buzzer tones. The industrial temperature rating tolerates factory-cabinet environments, and the bus matrix keeps display refresh independent of CAN traffic for a flicker-free UI.
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Test and Measurement Front-End
Test-and-measurement front-ends use the ATSAM3U4EA-AU as a data aggregator for ADC samples streamed over USB to a host PC. The 96 MHz core and DMA channels sustain sample rates suitable for low-bandwidth oscilloscope or data-logger channels, while 52 KB SRAM doubles as a circular buffer. The dual-bank Flash allows field-upgrade of the FPGA or sensor interface; USB-FS removes the need for a dedicated USB bridge IC.
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推薦產品摘要
工程參考資料，適用於 ATSAM3U4EA-AU — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ATSAM3U4EA-AUR | ATSAM3U4EA-CU | ATSAM3U2EA-AU |
|---|---|---|---|---|
| Package | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) - same | LQFP-144 (20x20 mm) - same | LQFP-144 (20x20 mm) - same |
| Brand | Microchip Technology | Microchip Technology - same | Microchip Technology - same | Microchip Technology - same |
| Core | ARM Cortex-M3 rev 2.0 | ARM Cortex-M3 rev 2.0 - same | ARM Cortex-M3 rev 2.0 - same | ARM Cortex-M3 rev 2.0 - same |
| Maximum Clock | 96 MHz | 96 MHz - same | 96 MHz - same | 96 MHz - same |
| Flash Memory | 256 KB dual-bank | 256 KB dual-bank - same | 256 KB dual-bank - same | 128 KB dual-bank (-50%) |
| SRAM | 52 KB | 52 KB - same | 52 KB - same | 36 KB (-31%) |
| USB | USB 2.0 Full-Speed Device | USB 2.0 Full-Speed Device - same | USB 2.0 Full-Speed Device - same | USB 2.0 Full-Speed Device - same |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C - same | Industrial -40C to +85C - same | Industrial -40C to +85C - same |
主要差異化特點
- Dual-bank Flash for safe in-application programming (對比ATSAM3U2EA-AU)
- Same die in tape-and-reel packaging code (對比ATSAM3U4EA-AUR)
- Industrial temperature-grade pin-compatible variant (對比ATSAM3U4EA-CU)
設計說明
Place a 100 nF ceramic decoupling capacitor as close as possible to every VDDIO and VDDCORE pin, and add a bulk 4.7 uF to 10 uF tantalum or ceramic on the main 3.3V rail. The SAM3U's internal voltage regulator (VDDOUT) requires its own 1 uF + 100 nF pair; insufficient decoupling causes VDDOUT ripple and code-fetch failures at 96 MHz. Brown-out detection (BOD) is enabled by default at 1.62V - leave it on unless an external supervisor overrides it.
Use a continuous ground plane beneath the LQFP-144 footprint and route USB DP/DM as a 90 ohm differential pair of matched length to the connector, keeping the pair over unbroken ground. Place the 12 MHz crystal within 5 mm of XIN/XOUT with short, symmetric traces and a guard ring tied to ground. Avoid routing high-speed signals (SPI, USB) under the crystal or across plane splits; this prevents reference spurs and EMI re-radiation.
Do not assume Flash executes in zero wait-state from cold boot - the flash accelerator remapping sequence must be enabled in software after reset, otherwise code runs at reduced speed. Watch-dog timer is enabled by default and locks the JTAG interface after a timeout in some configurations - clear the WDT and unlock the JTAG lock-bit during early firmware bring-up. Also note that the 144-pin variant has five VDDIO domains; tying all to 3.3V is acceptable but partial power-down of unused domains saves quiescent current.
合規資訊
RoHS and lead-free per Microchip product page. AEC-Q100 not applicable (industrial MCU, not automotive qualified). REACH compliance per Microchip declaration.
