DSPIC33CH128MP506-I/PT - Dual-Core 100MHz DSC, 128KB Flash, TQFP-64 | Microchip
MPN： DSPIC33CH128MP506-I/PT ✓ 啟用中DSPIC33CH128MP506-I/PT 概覽
A Digital Signal Controller (DSC) is a hybrid MCU/DSP that combines the deterministic interrupt response of a microcontroller with the single-cycle MAC engine and DSP-oriented instruction set of a digital signal processor. Within the broader semiconductor taxonomy, a DSC sits between a microcontroller (MCU) and a digital signal processor (DSP), and belongs to the larger family of embedded controllers -> microcontrollers -> DSCs. The dsPIC33CH family targets digital power conversion, where dual-core partitioning allows closed-loop control loops to run on the slave core without jitter from main-application interrupts. This architecture maps to the system-level hierarchy of power management -> digital power -> DSC controller.
Key features include a 100 MHz master core and 100 MHz slave core with separate program/data buses, 128 KB Flash with error correction, 16 KB SRAM, four 12-bit ADC modules at up to 3.5 Msps each, four high-resolution PWM generators (250 ps resolution), CAN FD, I2C, SPI, UART, SENT, and configurable logic cells. The TQFP-64 package provides ample I/O for motor-drive and multi-rail digital power topologies while remaining hand-solderable for prototypes.
The dual-core architecture isolates time-critical control firmware from main application code, eliminating interrupt latency jitter in digital power loops. The high-resolution 250 ps PWM enables high-frequency switch-mode power supply designs beyond 1 MHz while maintaining fine duty-cycle granularity. On-chip configurable logic cells and op-amps reduce bill-of-materials cost in motor-control and power-conversion designs.
Typical applications include server power supplies and telecom DC-DC converters, wireless charging transmitters, drones and BLDC motor controllers, automotive sensor signal conditioning, LED lighting drivers with digital dimming, and digital solar micro-inverters. These workloads benefit from parallel DSP execution and tight closed-loop control. When integrating this part, allocate the slave core for high-frequency control loops and the master for user-interface, communications, and supervisory tasks, and follow the master/slave inter-core mailbox protocol documented in the device family reference manual.
直接替換替代品，適用於 DSPIC33CH128MP506-I/PT — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： DSPIC33CH128MP506-I/PT （相同外形與佔位） — 差異在於 Package, Core Architecture, Operating Temperature, High-Resolution PWM, Program Memory (Flash).
DSPIC33CH128MP506-H/PT
✅ 直接替換📋 參考替代品（不在目錄中）
DSPIC33CH128MP506-I/M4
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
DSPIC33CH128MP206-I/PT
✅ 直接替換聯絡詢價
查看資料表 →DSPIC33CH128MP208T-I/PT
✅ 直接替換聯絡詢價
查看資料表 →DSPIC33CH128MP506-I/PT 最大額定值與電氣特性
| Core Architecture | Dual-core dsPIC33C DSC (master + slave) |
| Core Frequency (Master) | 100 MHz |
| Core Frequency (Slave) | 100 MHz |
| Program Memory (Flash) | 128 KB |
| Data Memory (RAM) | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| ADC | 4x 12-bit, up to 3.5 Msps |
| High-Resolution PWM | 4 generators, 250 ps resolution |
| CAN | CAN FD |
| 封裝 | TQFP-64 (10x10 mm) |
| 工作溫度 | -40 C to +85 C (industrial grade -I) |
| 安裝類型 | Surface Mount |
| MSL 等級 | 3 (168 hours) |
| RoHS 狀態 | Compliant |
| Total GPIO (approx.) | 53 (per TQFP-64) |
DSPIC33CH128MP506-I/PT 腳位配置
| 腳位 1 | RP55/ASDA1/SCK1 — Remappable I/O / SPI clock (alt function) |
| 腳位 2 | RP54/ASDA2/SDO2 — Remappable I/O / SPI data out (alt) |
| 腳位 3 | RP53/ASCL1/SDA1 — Remappable I/O / I2C data (alt) |
| 腳位 4 | RP49/TDI — JTAG TDI / remappable I/O |
| 腳位 5 | RP48/TCK — JTAG TCK / remappable I/O |
| 腳位 6 | RP47/TDO — JTAG TDO / remappable I/O |
| 腳位 7 | RP52/TMS — JTAG TMS / remappable I/O |
| 腳位 8 | OSCI — Crystal oscillator input |
| 腳位 9 | OSCO — Crystal oscillator output |
| 腳位 10 | VDD — Digital supply 3.0-3.6 V |
| 腳位 11 | VSS — Digital ground |
| 腳位 12 | PGEC1 — ICSP clock (pair 1) |
| 腳位 13 | PGED1 — ICSP data (pair 1) |
| 腳位 14 | MCLR — Master clear / reset (active low) |
| 腳位 15 | RP46/PWM4H — Remappable I/O / PWM4 high output |
| 腳位 16 | RP45/PWM4L — Remappable I/O / PWM4 low output |
| 腳位 17 | RP44/PWM3H — Remappable I/O / PWM3 high output |
| 腳位 18 | RP43/PWM3L — Remappable I/O / PWM3 low output |
| 腳位 19 | RP42/PWM2H — Remappable I/O / PWM2 high output |
| 腳位 20 | RP41/PWM2L — Remappable I/O / PWM2 low output |
| 腳位 21 | RP40/PWM1H — Remappable I/O / PWM1 high output |
| 腳位 22 | RP39/PWM1L — Remappable I/O / PWM1 low output |
| 腳位 23 | VDD — Digital supply 3.0-3.6 V |
| 腳位 24 | VSS — Digital ground |
| 腳位 25 | AN13/RP34/C1IN2 — Analog input 13 / remappable I/O / comparator input |
| 腳位 26 | AN14/RP35/C1IN3 — Analog input 14 / remappable I/O / comparator input |
| 腳位 27 | AN15/RP36/C1IN4 — Analog input 15 / remappable I/O / comparator input |
| 腳位 28 | AVSS — Analog ground |
| 腳位 29 | AVDD — Analog supply 3.0-3.6 V |
| 腳位 30 | AN0/C1IN1 — Analog input 0 / comparator input 1 |
| 腳位 31 | AN1 — Analog input 1 |
| 腳位 32 | AN2 — Analog input 2 |
| 腳位 33 | AN3 — Analog input 3 |
| 腳位 34 | AN4 — Analog input 4 |
| 腳位 35 | AN5 — Analog input 5 |
| 腳位 36 | AN6 — Analog input 6 |
| 腳位 37 | AN7 — Analog input 7 |
| 腳位 38 | VREF+ — ADC voltage reference high |
| 腳位 39 | VREF- — ADC voltage reference low |
| 腳位 40 | AVDD — Analog supply 3.0-3.6 V |
| 腳位 41 | AVSS — Analog ground |
| 腳位 42 | C1IN1+/C2IN1+ — Comparator 1/2 non-inverting input |
| 腳位 43 | C1IN1-/C2IN1- — Comparator 1/2 inverting input |
| 腳位 44 | C1OUT/C2OUT — Comparator 1/2 output |
| 腳位 45 | RP32/PWM5H — Remappable I/O / PWM5 high output |
| 腳位 46 | RP33/PWM5L — Remappable I/O / PWM5 low output |
| 腳位 47 | RP38/C1TX — Remappable I/O / CAN FD transmit |
| 腳位 48 | RP37/C1RX — Remappable I/O / CAN FD receive |
| 腳位 49 | RP56/ASCL2/SCL2 — Remappable I/O / I2C clock (alt) |
| 腳位 50 | RP57/ASDA2/SDA2 — Remappable I/O / I2C data (alt) |
| 腳位 51 | RP58/SDI1 — Remappable I/O / SPI data in |
| 腳位 52 | RP59/SDO1 — Remappable I/O / SPI data out |
| 腳位 53 | RP60/SCK1 — Remappable I/O / SPI clock |
| 腳位 54 | RP61/U1RX — Remappable I/O / UART1 RX |
| 腳位 55 | RP62/U1TX — Remappable I/O / UART1 TX |
| 腳位 56 | RP63/U2RX — Remappable I/O / UART2 RX |
| 腳位 57 | RP64/U2TX — Remappable I/O / UART2 TX |
| 腳位 58 | PGEC2 — ICSP clock (pair 2) |
| 腳位 59 | PGED2 — ICSP data (pair 2) |
| 腳位 60 | PGEC3 — ICSP clock (pair 3) |
| 腳位 61 | PGED3 — ICSP data (pair 3) |
| 腳位 62 | VDD — Digital supply 3.0-3.6 V |
| 腳位 63 | VSS — Digital ground |
| 腳位 64 | VDD — Digital supply 3.0-3.6 V |
典型應用
DSPIC33CH128MP506-I/PT 適用於 6 應用s: Server & Telecom Digital Power Supplies, Wireless Charging Transmitters, BLDC / PMSM Motor Control (Drones, Robotics, E-Bike), Automotive Sensor Signal Conditioning, Digital LED Lighting Drivers, Solar Micro-Inverters & Optimizers.
Server & Telecom Digital Power Supplies
The DSPIC33CH128MP506-I/PT is purpose-built for high-density server and telecom DC-DC converters operating above 500 kHz switching frequency. Its 250 ps high-resolution PWM enables duty-cycle granularity below 0.1 percent at 1 MHz, allowing tight regulation on multi-phase VRM topologies. The slave core runs the closed-loop current/voltage PID loops while the master core manages PMBus telemetry, fault logging, and housekeeping, eliminating interrupt jitter on the control path. Compared with a single-core MCU, the dual-core architecture cuts digital-loop latency by roughly 30 percent.
推薦
Wireless Charging Transmitters
Qi-compliant and proprietary resonant wireless power transmitters use the DSPIC33CH128MP506-I/PT for foreign-object detection, coil current zero-crossing detection, and real-time closed-loop power tuning. The slave core samples the resonant tank current at 3.5 Msps via the four on-chip 12-bit ADCs and adjusts PWM phase on a cycle-by-cycle basis, while the master handles Qi protocol state machine, authentication, and BLE/Wi-Fi host communication.
推薦
BLDC / PMSM Motor Control (Drones, Robotics, E-Bike)
Field-oriented control (FOC) of brushless DC and PMSM motors benefits from the dual-core partitioning of the DSPIC33CH128MP506-I/PT. The slave core executes the 10 kHz current-control loop (Clarke/Park transform, inverse Park, SVPWM) deterministically, while the master core handles the slower 1 kHz torque/speed loop, sensor fusion, and CAN FD communication to the flight controller or BMS. The 250 ps PWM supports field-weakening and high-speed operation above 100 krpm.
推薦
Automotive Sensor Signal Conditioning
The DSPIC33CH128MP506-I/PT can serve as an automotive sensor ECU for battery management or chassis sensing, processing analog inputs from current shunts, thermistors, and accelerometers. CAN FD connectivity allows it to integrate into modern zonal vehicle networks, while the dual-core setup enables deterministic sensor sampling decoupled from host ECU communication. Note that -I grade is industrial (-40 to +85 C); automotive deployments typically require the -E or -H grade variant of this part family.
推薦
Digital LED Lighting Drivers
High-end architectural and horticulture LED drivers use the DSPIC33CH128MP506-I/PT for multi-channel constant-current control with sub-1 percent dimming accuracy. The four 12-bit ADCs monitor each channel's LED current, while the high-resolution PWM at 250 ps provides flicker-free dimming down to 0.1 percent duty cycle. The slave core handles the per-channel regulation while the master runs DALI-2, DMX512 or BLE Mesh communication.
推薦
Solar Micro-Inverters & Optimizers
Module-level solar micro-inverters and DC power optimizers use the DSPIC33CH128MP506-I/PT to implement MPPT algorithms, islanding detection, and grid-tie synchronization. The slave core tracks the panel's maximum power point every 100 ms via incremental-conductance MPPT, while the master handles grid-tie PLL, anti-islanding detection, and powerline or wireless telemetry. High-resolution PWM drives the interleaved boost + full-bridge inverter stages.
推薦
推薦產品摘要
工程參考資料，適用於 DSPIC33CH128MP506-I/PT — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | DSPIC33CH128MP506-H/PT | DSPIC33CH128MP206-I/PT | DSPIC33CH128MP208T-I/PT |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | TQFP-64 (10x10 mm) | TQFP-64 (10x10 mm) - same | TQFP-64 (10x10 mm) - same | TQFP-64 (10x10 mm) - same |
| Core Architecture | Dual-core dsPIC33C | Dual-core dsPIC33C | Dual-core dsPIC33C | Dual-core dsPIC33C |
| Core Frequency | 100 MHz master + 100 MHz slave | 100 MHz master + 100 MHz slave | 100 MHz master + 100 MHz slave | 100 MHz master + 100 MHz slave |
| Flash Memory | 128 KB | 128 KB | 64 KB (-50%) | 128 KB |
| RAM | 16 KB | 16 KB | 8 KB (-50%) | 16 KB |
| High-Resolution PWM | 250 ps, 4 generators | 250 ps, 4 generators | 250 ps, 4 generators | 250 ps, 8 generators |
| CAN FD | Yes | Yes | Yes | Yes |
| Operating Temperature | -40 C to +85 C (-I grade) | -40 C to +150 C (-H grade) | -40 C to +85 C | -40 C to +85 C |
| Approx. Unit Price (qty-1, as of 2026-09-22) | $9.85 | ~$11.50 | ~$7.20 | ~$10.50 |
主要差異化特點
- Dual-core partitioning eliminates jitter on closed-loop control tasks (對比Single-core dsPIC33EP256MC506)
- High-resolution 250 ps PWM duty-cycle resolution (對比Standard 8.32 ns PWM on dsPIC33EP family)
- Up to 4x 12-bit ADCs at 3.5 Msps each (對比1x ADC on dsPIC33EP256MC506)
設計說明
Estimated: The DSPIC33CH128MP506-I/PT operates from 3.0 V to 3.6 V. Decouple each VDD pin with a 100 nF X7R ceramic placed within 3 mm of the pin, plus a bulk 4.7 uF or 10 uF ceramic. Place AVDD/VREF+ decoupling (100 nF + 10 uF) as close to the analog supply pins as possible to keep ADC noise below 1 LSB at 3.5 Msps.
Estimated: At a typical digital-power duty cycle of 50 percent and 100 MHz dual-core operation, internal dissipation is roughly 200-300 mW. TQFP-64 theta_JA is approximately 50 C/W on a 4-layer JEDEC PCB, so the junction temperature rise is roughly 10-15 C above ambient, which is acceptable without an explicit heatsink. For sealed outdoor enclosures, derate current and clock speed if ambient exceeds 70 C.
Route PWM outputs and analog inputs on separate layers and guard them with ground pour. Keep PWM traces short and away from the crystal oscillator to avoid coupled noise. Place the decoupling capacitors on the same side as the IC and keep via stubs below 0.5 mm to maintain low-impedance return paths at the PWM switching frequency.
Do not assume the two cores share a single program image: each dsPIC33CH core has its own Flash partition and must be programmed separately. Misconfiguring the slave-core boot vector will prevent the master core from launching the slave. Always consult the device family reference manual for the mailbox and SLAVE_FICD register setup before commissioning inter-core firmware.
合規資訊
RoHS compliant per Microchip product page. -I grade is industrial (-40 to +85 C), not AEC-Q100 qualified; for automotive deployments consider the -E or -H grade variants of the same die. BitLocker may be branded in some regions.
