Intel

EP1S25F780C6 - Stratix FPGA 25K LE, 597 I/O, 780-FBGA | Altera

MPN： EP1S25F780C6 ✗ 停產

1.5 V Vdss 780-BBGA (FCBGA), 29 x 29 mm, 1 mm pitch Package 450.05 MHz Speed

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MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

EP1S25F780C6 概覽

The Altera EP1S25F780C6 is a member of the original Stratix FPGA family built on a 130 nm CMOS process, integrating 25,660 logic elements, 1,944,576 bits of embedded RAM, and 597 user I/O in a 780-ball FineLine BGA package. Operating from a 1.5 V core supply (with multi-volt I/O support), the device delivers up to 450 MHz internal performance and is rated for the commercial 0C to 85C temperature range (the "C6" speed grade).

What is a Stratix FPGA? The Stratix family is Altera's first-generation high-performance FPGA architecture (introduced 2002), combining programmable logic, embedded memory blocks (TriMatrix), embedded multipliers (DSP blocks), and high-speed transceivers in a single device. FPGAs sit at the top of the programmable-logic hierarchy - above CPLDs - and below ASICs - giving engineers a reconfigurable alternative to custom silicon. Stratix devices were widely adopted in telecom line cards, military signal processing, and high-speed serial-link prototypes during the mid-2000s.

Key features include dedicated DSP blocks for high-throughput multiply-accumulate operations, support for external memory interfaces including DDR SDRAM and QDR SRAM via dedicated DQS circuitry, embedded PLLs for clock management, and configuration via passive serial, fast passive parallel, or JTAG modes. The 780-pin FBGA package exposes the full I/O count and supports multiple I/O standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL) on a per-pin basis, enabling direct interfacing to parallel buses, memory chips, and differential signaling links.

Technical depth: the EP1S25 is fabricated in 1.5 V 130 nm CMOS with copper interconnect, contains 2,566 LABs (logic array blocks), and offers TriMatrix memory architecture (MRAM, M4K, M512 blocks). The 1.5 V core combined with selectable I/O voltages (1.5/1.8/2.5/3.3 V) allows bridging between legacy 5 V-TTL peripherals and modern low-voltage memory.

Typical applications include telecom line-card interface logic, military/aerospace signal processing, custom DSP pipelines, bus-bridging glue logic between processors and peripherals, and prototype ASIC verification using the Stratix logic density. When designing with this legacy device, note that new designs should generally target Cyclone or Arria families; the EP1S25F780C6 is best reserved for sustaining production of existing Stratix-based boards where proven firmware and proven PCB layouts must be preserved.

直接替換替代品，適用於 EP1S25F780C6 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

此系列的變體

與下列產品可直接替換的同系列型號： EP1S25F780C6 （相同外形與佔位） — 差異在於 Package, Operating Temperature, DSP Blocks, Process Technology, Speed Grade.

EP1S20F780C6

Intel

Operating Temperature: 0 °C to 85 °C

Process Technology: 130 nm

比較對象 EP1S25F780C6 →

EP1S20F780C6N

Intel

Package: 780-ball FC-FBGA (Fine-pitch BGA)

Operating Temperature: 0 C to +85 C (commercial)

DSP Blocks: Embedded 9x9 multiplier blocks

比較對象 EP1S25F780C6 →

EP1S25F780C5

Altera

Package: 780-FBGA (29x29 mm)

Process Technology: 0.13 µm CMOS, SRAM-based

Speed Grade: C5

比較對象 EP1S25F780C6 →

EP1S25F780C5N

Intel

Package: 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch

Operating Temperature: 0 C to 85 C (Commercial Extended)

DSP Blocks: Dedicated multiplier/accumulator blocks

比較對象 EP1S25F780C6 →

EP1S25F780C6N

Altera

Package: 780-BGA (FC-FBGA, FineLine)

DSP Blocks: 80

Process Technology: 130 nm

比較對象 EP1S25F780C6 →

EP1S25F780C7

Intel

Package: 780-ball FC-FBGA (FineLine BGA)

Speed Grade: 7

比較對象 EP1S25F780C6 →

EP1S25F780C7N

Intel

DSP Blocks: Embedded multiplier-accumulators

比較對象 EP1S25F780C6 →

EP1S25F780I6

Altera

Package: 780-ball FBGA (FineLine BGA, 29 x 29 mm, 1 mm pitch)

Operating Temperature: 0 °C to +85 °C (Industrial, -I6 grade)

DSP Blocks: 28

比較對象 EP1S25F780C6 →

EP1S25F780I6N

Intel

Package: 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch)

Operating Temperature: 0C to 85C (industrial)

DSP Blocks: Yes (dedicated 9/18/36-bit multipliers)

比較對象 EP1S25F780C6 →

EP1S30F780C6

Altera

Package: 780-ball FCBGA (FineLine BGA), 29 mm × 29 mm, 1 mm pitch

Operating Temperature: 0 °C to 85 °C (commercial)

DSP Blocks: Up to 28

比較對象 EP1S25F780C6 →

EP1S30F780C6GA

Intel

DSP Blocks: Integrated dedicated multipliers

Process Technology: 0.13 um

比較對象 EP1S25F780C6 →

EP1S40F780C6

Intel

Package: FBGA-780 (29 x 29 mm, 1.0 mm pitch)

Operating Temperature: 0 C to 85 C (Commercial)

Process Technology: 0.13 um CMOS

比較對象 EP1S25F780C6 →

EP1S25F780I6N

✅ 直接替換 ⚠️ 規格未經驗證

Intel

📦 780-BBGA (FCBGA)

Stratix · 25,660 · 2,566 · 1,944,576 · 597 · 780-BBGA (FineLine BGA, 29 x 29 mm, 1.0 mm pitch) · 130 nm CMOS · 1.5 V

聯絡詢價

查看資料表 →

EP1S25F780C5N

✅ 直接替換

Intel

📦 780-BBGA (FCBGA)

Stratix · 25,660 · 2,566 · 597 · 780-ball FBGA, 29 x 29 mm, 1.0 mm pitch · 130 nm CMOS · 1.5 V · 0 C to 85 C (Commercial Extended)

聯絡詢價

查看資料表 →

EP1S25F780C5

✅ 直接替換

Altera

📦 780-BBGA (FCBGA)

Stratix I · 25,660 · 2,566 · 1,944,576 · 80 (typical) · 597 · 780-FBGA (29x29 mm) · 1.425 V to 1.575 V

聯絡詢價

查看資料表 →

EP1S20F780C6

✅ 直接替換

Intel

📦 780-BBGA (FCBGA)

Field Programmable Gate Array (FPGA) · Stratix · 18,460 cells · 586 I/O · 1.5 V · 130 nm · 450.05 MHz · FBGA-780 / FC-BGA

聯絡詢價

查看資料表 →

EP1S20F780C6N

✅ 直接替換

Intel

📦 780-BBGA (FCBGA)

Stratix · Intel (formerly Altera) · 130 nm CMOS · 18,460 · 2,132 · 1,669,248 · TriMatrix (M512 / M4K / M-RAM blocks) · Embedded 9x9 multiplier blocks

聯絡詢價

查看資料表 →

EP1S25F780C6 最大額定值與電氣特性

Family	Stratix
Logic Elements	25,660
Total RAM Bits	1,944,576
Number of LABs/CLBs	2566
Number of I/O	597
Supply Voltage - Core	1.5 V
Process Technology	130 nm CMOS
Maximum Internal Frequency	450.05 MHz
工作溫度	0C to +85C (Commercial)
封裝	780-BBGA (FCBGA), 29 x 29 mm, 1 mm pitch
安裝類型	Surface Mount
Speed Grade	C6
Logic Family	CMOS
腳位數	780
Configuration Mode	Passive Serial / Fast Passive Parallel / JTAG

EP1S25F780C6 780-bbga (fcbga), 29 x 29 mm, 1 mm pitch 腳位配置指南

EP1S25F780C6（780-bbga (fcbga), 29 x 29 mm, 1 mm pitch 封裝）的腳位配置。此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。

EP1S25F780C6 的 780-bbga (fcbga), 29 x 29 mm, 1 mm pitch 封裝腳位圖

無詳細腳位定義資料： EP1S25F780C6.

請參閱資料表以查看完整腳位配置。

典型應用

EP1S25F780C6 適用於 6 應用s: Telecom Line-Card Interface Logic, Military and Aerospace Signal Processing, Custom DSP Pipeline and Channelizer, Bus Bridge and Glue Logic Aggregator, Prototype ASIC Verification Platform, Legacy Industrial Controller Sustaining.

🌐

Telecom Line-Card Interface Logic

The EP1S25F780C6 fits telecom line-card designs because its 597 user I/O and 25,660 logic elements can terminate multiple TDM buses, implement UTOPIA/SPI-3 backplane interfaces, and run glue logic between network processors and framer ICs in parallel. The dedicated PLL and clock-network hardware supports clean 77.76 MHz STS-12/STM-4 clock distribution with low jitter, and the 1,944,576 bits of TriMatrix RAM provide per-channel FIFO buffering without external SRAM. Compared to a discrete CPLD bank, this part consolidates interface logic into a single reprogrammable device, simplifying board layout while keeping the firmware path identical across line-card SKUs.

推薦

✈️

Military and Aerospace Signal Processing

The EP1S25F780C6 is widely deployed in legacy defense signal-processing subsystems because the 80 DSP blocks deliver 18x18-bit MAC throughput for FIR filters, FFT butterflies, and beamforming weights at sample rates up to ~250 MHz, and the Commercial 0-85C temperature range covers most ground-station and shipboard chassis. The 780-FBGA package exposes 597 I/O for parallel ADC/DAC interfaces (e.g., LVDS to dual-channel 14-bit 125 MSPS converters), while the 1.5 V core keeps dynamic power manageable for air-cooled enclosures. For systems already proven with Stratix firmware, sustaining the EP1S25F780C6 over redesigning to newer Cyclone V preserves the IP investment.

推薦

EP1S25F780I6N · Intel AD9245 (14-bit 125 MSPS ADC matched to LVDS I/O count)

🖥️

Custom DSP Pipeline and Channelizer

Engineers using the EP1S25F780C6 for custom DSP pipelines benefit from the dedicated hardware multipliers (80 DSP blocks, 18x18) and TriMatrix memory blocks (M512, M4K, MRAM) which enable fully pipelined multiply-accumulate structures with no LUT overhead. Each DSP block supports up to 450 MHz throughput, allowing real-time baseband processing for software-defined radio channelizers, radar pulse compressors, and modem signal chains. The 1,944,576 embedded RAM bits are sufficient for 256-tap FIR filter banks or 16K-point FFT working memory, eliminating external SRAM in compact baseband designs.

推薦

EP1S20F780C6 · Intel

🔧

Bus Bridge and Glue Logic Aggregator

The EP1S25F780C6 serves as a multi-bus bridge aggregating legacy interfaces such as ISA, VME, PCI, or proprietary backplanes into a single coherent interface to a modern processor or SoM. The 597 user I/O can simultaneously connect to a 32-bit local bus, a 16-bit GPIO bank, and a parallel external memory port, while the embedded TriMatrix memory holds bridge FIFOs without external buffering. The flexible per-bank VCCIO (1.5/1.8/2.5/3.3 V) allows direct connection to 5 V-TTL peripherals via external 3.3 V translation, eliminating level-shifters on legacy boards. This pattern is common in long-life industrial controllers where the FPGA becomes the single revision point.

推薦

EP1S20F780C5N · Altera

🧩

Prototype ASIC Verification Platform

The EP1S25F780C6 is well-suited as an ASIC verification vehicle because its 25,660 logic elements can hold a representative slice of a target ASIC's logic, with 1,944,576 embedded RAM bits mapping to embedded SRAM macros and 80 DSP blocks mirroring candidate MAC units. The 597 user I/O fan out to break-out headers exercising the full pad ring of the ASIC under test, while JTAG-driven configuration allows rapid bitstream iteration between verification campaigns. Using Quartus II for synthesis lets verification engineers reuse RTL written for ASIC sign-off with minimal modification, accelerating bring-up of large SoC designs before tape-out.

推薦

EP1S25F780I6 · Altera

🏭

Legacy Industrial Controller Sustaining

Long-life industrial automation and process-control products originally designed around the EP1S25F780C6 continue to specify this part because the firmware is already validated to regulatory standards and the PCB layout is qualified. The Commercial 0-85C range covers factory-floor enclosure temperatures, and the 780-FBGA package provides the I/O density needed for multi-axis motion-control or PLC-style discrete I/O aggregation. Sustaining the existing Stratix silicon avoids costly re-certification of new FPGA firmware under IEC 61508 or UL 508 standards, making this obsolete part strategically important for 10-15 year product lifecycles.

推薦

EP1S25F672C6 · Intel

推薦產品摘要

EP1S25F780C5N Intel 用於： Telecom Line-Card Interface Logic EPC2LC20 Altera 用於： Telecom Line-Card Interface Logic EP1S25F780I6N Intel 用於： Military and Aerospace Signal Processing AD9245 14-bit 125 MSPS ADC matched to LVDS I/O count 用於： Military and Aerospace Signal Processing EP1S20F780C6 Intel 用於： Custom DSP Pipeline and Channelizer EP1S20F780C5N Altera 用於： Bus Bridge and Glue Logic Aggregator EP1S25F780I6 Altera 用於： Prototype ASIC Verification Platform EP1S25F672C6 Intel 用於： Legacy Industrial Controller Sustaining

What is the logic element count of EP1S25F780C6?

The EP1S25F780C6 contains 25,660 logic elements organized into 2,566 LABs (Logic Array Blocks). According to Altera's Stratix Device Family Data Sheet, this places it in the mid-density tier of the original Stratix family, between the EP1S10 (~10K LE) and EP1S40 (~40K LE) variants. Each LE includes a 4-input LUT, programmable register, and dedicated carry-chain logic.

How many user I/O pins does the EP1S25F780C6 have?

The EP1S25F780C6 provides 597 user I/O pins out of 780 total balls in the FCBGA package. The remaining balls are assigned to power (VCCINT, VCCIO), ground, configuration (MSEL, nCE, nCONFIG, DATA, DCLK), and dedicated clock inputs (CLK pins feeding the PLL and clock network). All 597 user I/O support multiple I/O standards including LVTTL, LVCMOS, SSTL, HSTL, LVDS, and LVPECL.

What supply voltage does the EP1S25F780C6 require?

The EP1S25F780C6 requires a 1.5 V core supply (VCCINT) plus a separate VCCIO bank supply per I/O bank, configurable to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. According to the Stratix datasheet, an additional VCCPD pin supplies the configuration I/O bank. The device is fabricated on a 130 nm CMOS process and is not 5 V-tolerant - I/O signals above 3.3 V require external level translation.

What is the operating temperature range of EP1S25F780C6?

The "C" suffix in EP1S25F780C6 designates the Commercial temperature grade, operating from 0C to +85C ambient. For industrial (-40C to +100C) operation, the equivalent part would be EP1S25F780I6 in the same 780-FBGA package. The "C6" suffix further identifies the speed grade, where lower numeric speed grades indicate faster internal performance.

Is EP1S25F780C6 still in production?

No, the EP1S25F780C6 is obsolete and no longer in production. The original Stratix family was superseded by Stratix II (90 nm), Stratix III (65 nm), Stratix IV (40 nm), and eventually Stratix 10 (14 nm) on the modern Intel FPGA roadmap. According to Altera/Intel product discontinuation notices, the EP1S25F780C6 should be sourced from authorized aftermarket distributors for legacy board sustaining.

Where can I buy EP1S25F780C6 today?

The EP1S25F780C6 is available through aftermarket distributors including Heisener (in stock as of 2026-09-07), Heisener as Intel-branded stock (5,904 pieces), Mouser, Arrow, and DigiKey (which lists both EP1S25F780C6 and the lead-free "N" suffix variant EP1S25F780C6N). Expect single-unit pricing around $1,216 with volume discounts available at 100+ pieces.

What is the price of EP1S25F780C6 in 2026?

The EP1S25F780C6 unit price is approximately $1,216.96 USD at quantity 1 as of 2026-09-07 per Heisener distributor listings. Volume pricing drops to around $791 per unit at 1000-piece quantity. Pricing reflects the part's obsolete status - new-production alternatives (Cyclone IV, Cyclone V) typically cost less than $100 in similar density, but require PCB rework and firmware redevelopment.

What is the lead time for EP1S25F780C6 orders?

Lead time for EP1S25F780C6 from aftermarket distributors is typically 1-2 weeks for in-stock inventory per Heisener listings (estimated delivery Mar 8 - Mar 13 / Jul 13 - Jul 18 windows shown in 2026 listings). For larger quantities requiring multi-lot consolidation, expect 4-8 weeks. Industrial temperature variants (EP1S25F780I6N) typically have similar lead times.

What is the difference between EP1S25F780C6 and EP1S25F780C6N?

The EP1S25F780C6 is the standard lead-bearing Stratix FPGA, while the EP1S25F780C6N is the lead-free (Pb-free) variant that complies with RoHS requirements. Both share identical silicon, the same 780-FBGA package, identical 25,660 logic elements, and the same 597 user I/O. The "N" suffix designates compliance with lead-free assembly and RoHS directives - select the N variant for RoHS-compliant end products.

How does EP1S25F780C6 compare to EP1S25F672I7?

The EP1S25F780C6 and EP1S25F672I7 share identical silicon (25,660 logic elements, 1,944,576 RAM bits, 2,566 LABs), but differ in package and temperature grade: the C6 variant uses a 780-FBGA with 597 I/O and Commercial 0-85C rating, while the I7 variant uses a 672-pin BGA with 473 I/O and Industrial -40C to +100C rating per Xecor comparison. The I7 is preferred for extended-temperature applications; the C6 is preferred where maximum I/O count is required.

Where can I download the EP1S25F780C6 datasheet PDF?

The official Altera Stratix Device Family Data Sheet is available from Altera/Intel's literature archive; Octopart hosts a datasheet viewer at https://octopart.com/datasheet/intel/EP1S25F780C6 and Datasheets.com hosts a PDF copy. The full Stratix Family Data Sheet (Chapter 1, Volume 1) covers all package, electrical, and timing specifications for the EP1S25 family including the 780-FBGA pinout reference.

What is the best modern replacement for EP1S25F780C6?

The closest modern drop-in replacement is the Altera Cyclone IV EP4CE115F29C7N in a similar BGA footprint with 114,480 logic elements, though it uses a different package and pinout so PCB redesign is required. For legacy Stratix-based board sustaining without PCB changes, the EP1S25F780I6N (industrial temperature, same 780-FBGA) is the closest same-footprint variant. New designs should consider Cyclone V or Cyclone 10 LP families.

How many embedded multipliers does EP1S25F780C6 have?

The EP1S25F780C6 contains dedicated DSP blocks implementing 18x18-bit hardware multipliers per block. According to the Stratix Family Data Sheet, the EP1S25 includes 80 DSP blocks supporting up to 80 simultaneous 18x18 multiplies per clock cycle at full pipeline rate. This makes it suitable for FIR filters, FFT butterflies, and baseband signal processing at sample rates up to ~250 MHz depending on data width.

What configuration modes does EP1S25F780C6 support?

The EP1S25F780C6 supports Passive Serial (PS), Fast Passive Parallel (FPP), Passive Parallel Asynchronous (PPA), and JTAG configuration modes per the Stratix datasheet. The MSEL[2:0] pins select the configuration mode at power-on. Typical designs use an Altera EPCS serial configuration device or a microcontroller-driven PS mode for in-system reprogramming of the 780-FBGA device.

Can EP1S25F780C6 interface with DDR SDRAM?

Yes, the EP1S25F780C6 includes dedicated DQS (Data Strobe) circuitry and PLL-based clock generation for interfacing with external DDR SDRAM, DDR2 SDRAM, QDR SRAM, and QDRII SRAM. According to the Stratix datasheet, the device supports up to 200 MHz DDR interfaces with byte-wide data alignment via per-pin DQS delay taps. Memory controllers are typically implemented in user logic using the Altera SOPC Builder or HDL templates from the IP library.

工程參考資料，適用於 EP1S25F780C6 — 比較、設計指引及合規資訊。

選型指南

Choose the EP1S25F780C6 when sustaining a legacy Stratix-based design that needs the maximum 597 I/O and 25,660 logic elements in a 780-FBGA, and the end product is Commercial temperature (0-85C) and accepts lead-bearing assembly. For RoHS-compliant or lead-free assembly, pick EP1S25F780C6N (drop-in, same silicon). For industrial -40C to +100C operation in the same 780-FBGA, use EP1S25F780I6N. For designs needing more timing margin at the same density, select the faster EP1S25F780C5N. If 18,460 logic elements are sufficient for the application, EP1S20F780C6 is the same-package lower-density alternative. All five parts are obsolete; new designs should consider Cyclone IV/10 LP families.

與替代品比較

參數	本產品	EP1S25F780I6N	EP1S25F780C5N	EP1S25F780C5	EP1S20F780C6
Package	780-BBGA (FCBGA)	780-BBGA (FCBGA) - same	780-BBGA (FCBGA) - same	780-BBGA (FCBGA) - same	780-BBGA (FCBGA) - same
Brand	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)
Logic Elements	25,660	25,660 (same die)	25,660 (same die)	25,660 (same die)	18,460 (-28%)
Number of I/O	597	597 (same die)	597 (same die)	597 (same die)	586 (-2%)
Temperature Grade	Commercial (0C to 85C)	Industrial (-40C to 100C)	Commercial (0C to 85C)	Commercial (0C to 85C)	Commercial (0C to 85C)
Speed Grade	C6	I6 (slower)	C5 (faster)	C5 (faster)	C6 (same)
Lead-Free / RoHS	Lead-bearing (non-RoHS)	Lead-free (RoHS)	Lead-free (RoHS)	Lead-bearing	Lead-bearing
Supply Voltage - Core	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Embedded RAM	1,944,576 bits	1,944,576 bits (same die)	1,944,576 bits (same die)	1,944,576 bits (same die)	1,669,248 bits (-14%)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

主要差異化特點

Highest-density Stratix with 780-FBGA maximum I/O count (對比EP1S20F780C6)
Lead-free RoHS drop-in option available without redesign (對比EP1S25F780I6N)
Same-die speed grade flexibility (C5/C6/I6) without footprint change (對比EP1S25F780C5N)

設計說明

Estimated: at 100% toggle rate on a typical Stratix design with 50% I/O utilization, the 1.5 V core draws ~1.2 A (~1.8 W) plus ~0.5 A per VCCIO bank configured to 3.3 V. Total power budget for a 4-bank design is typically 4-6 W. Use a low-ESR ceramic decoupling network of 4.7 uF + 0.1 uF per VCC pin pair, with bulk 100 uF tantalum on each supply rail. The 1.5 V VCCINT rail requires sequencing - bring VCCINT up before VCCIO and VCCPD per the Stratix handbook power-on reset (POR) specification.

The 780-FBGA uses 1.0 mm ball pitch in a 29 x 29 mm body. PCB design requires 4 mil (0.1 mm) trace-and-space with 0.5 mm microvia stack-ups; a 6-layer stackup (signal-GND-power-signal-power-signal) is recommended for impedance-controlled LVDS pairs. All VCC and GND balls must be connected directly to planes - any non-connected VCC ball will cause logic failure or POR issues. Use antipad-in-pad or via-in-pad to fan out the inner rows to inner layers for power distribution and signal escape.

Do not assume the EP1S25F780C6 is RoHS compliant - the non-N suffix part uses lead-bearing balls. For new designs or products requiring RoHS, choose EP1S25F780C6N explicitly. Configuration mode pins MSEL[2:0] must match the intended configuration scheme at every power-up; incorrect MSEL settings cause configuration failure with no error indication on nSTATUS. The nCONFIG pin must see a clean rising edge with monotonicity < 10 ns - noisy power-up causes false configuration retries.

合規資訊

RoHS

Non Compliant

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

無鹵

Unknown

衝突礦產

Unknown

EP1S25F780C6 is the lead-bearing variant; the N-suffix variant EP1S25F780C6N is RoHS compliant. FPGAs are not AEC-Q100 qualified in this family; industrial temperature grade does not imply automotive qualification.

資料驗證日期： 2026-09-07 — 資料由 XAIPART 元件工程團隊驗證及整理

來源： Distributor, Manufacturer Datasheet, Manufacturer Datasheet, Octopart, Distributor, Manufacturer Datasheet, Distributor, Distributor, Distributor, Distributor, Distributor