EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
MPN： EPM9320GC280-15 ✗ 停產EPM9320GC280-15 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device containing multiple PAL-like logic array blocks (LABs) interconnected by a programmable switch matrix; it sits between discrete PALs and FPGAs in the programmable-logic taxonomy. The MAX architecture places each macrocell between a logic array and an I/O pin, giving deterministic, predictable timing that is independent of internal routing - a property that distinguishes CPLDs from SRAM-based FPGAs and makes the MAX 9000 family well suited to control-plane and glue-logic applications.
Key features include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, programmable macrocell flip-flops with individual clear/preset, four pin feedback paths per I/O, and a JTAG Instruction Register supporting BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE, and USERCODE. The on-chip EEPROM cells provide zero-power standby (typically <100 mA quiescent) and instant-on operation without external boot devices.
Typical applications span high-density bus decoding, peripheral control, and state-machine replacement in industrial, telecom, and embedded systems where deterministic timing and non-volatility are required. Designers frequently pair the EPM9320 with SRAM, DRAM, and Flash controllers, bus bridges, and glue logic between microprocessors and peripherals.
When designing with the EPM9320GC280-15, allocate sufficient decoupling (100 nF + 10 uF near each supply pin) and route JTAG TMS/TCK/TDI/TDO with short traces to maintain ISP margin. Because the CPGA-280 package is socket-friendly but not reflow-compatible, plan board assembly around a PGA socket for rework flexibility.
This page consolidates distributor stock and pricing, drop-in alternatives sharing the CPGA-280 footprint, and applied design guidance not found in the original Altera datasheet alone, giving procurement and engineering teams a single source for EPM9320GC280-15 information.
直接替換替代品，適用於 EPM9320GC280-15 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM9320GC280-15 （相同外形與佔位） — 差異在於 Package, Usable Gates, Supply Voltage (VCC), Mounting Type, Architecture.
EPM9320GC280-15N
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EPM9320GC280-20
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM9320GC280-10
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
EPM9320BC356-15
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM9320GC280-15 最大額定值與電氣特性
| Family | MAX 9000 (EPM9320) |
| Device Type | CPLD - Complex Programmable Logic Device |
| Architecture | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Usable Gates | 6,000 |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 20 (16 macrocells per LAB) |
| Pin-to-Pin Propagation Delay | 15 ns |
| Maximum Internal Frequency | 117.6 MHz |
| Maximum User I/O Pins | 164 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| I/O Voltage Levels | 3.3 V or 5 V (configurable) |
| Programmability | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| 封裝 | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| 安裝類型 | Through-hole (PGA socket) |
| 工作溫度 | 0 C to +70 C (commercial) |
| MSL 等級 | 3 (168 hours) |
| RoHS 狀態 | ROHS3 compliant (per fpgalink listing) |
| Technology Node | CMOS EEPROM, third-generation MAX |
EPM9320GC280-15 腳位配置
| 腳位 1 | I/O — User I/O pin (function determined by design) |
| 腳位 70 | I/O — User I/O pin (function determined by design) |
| 腳位 140 | I/O — User I/O pin (function determined by design) |
| 腳位 210 | I/O — User I/O pin (function determined by design) |
| 腳位 280 | I/O — User I/O pin (function determined by design) |
| 腳位 J1 | TDI — JTAG Test Data In (IEEE 1149.1) |
| 腳位 J2 | TMS — JTAG Test Mode Select |
| 腳位 J3 | TCK — JTAG Test Clock |
| 腳位 J4 | TDO — JTAG Test Data Out |
| 腳位 GND_PINS | GND — Multiple ground pins distributed across PGA array |
| 腳位 VCC_PINS | VCC — Multiple 5 V supply pins distributed across PGA array |
典型應用
EPM9320GC280-15 適用於 6 應用s: High-Density Address Bus Decoder, ISA/PCI Bus Glue Logic, DSP and Microprocessor Peripheral Controller, Industrial Control State-Machine, Telecom Backplane Control Logic, Legacy Industrial Motherboard Replacement.
High-Density Address Bus Decoder
The EPM9320GC280-15's 320 macrocells and 164 user I/O pins make it ideal for decoding wide microprocessor address buses such as 32-bit 68000, VME, or 8086-family interfaces. With a deterministic 15 ns pin-to-pin delay (per the Altera MAX 9000 datasheet), the device generates chip-select and strobe signals well within a 25 MHz bus cycle, and its EEPROM non-volatility eliminates boot-time configuration. Place the EPM9320 adjacent to the memory bank with 100 nF + 10 uF decoupling and route JTAG pins to a 4-pin header for in-field ISP. Compared to discrete 22V10 PAL chains, a single EPM9320 replaces 10-20 PALs, simplifying the BOM.
推薦
ISA/PCI Bus Glue Logic
Legacy ISA and PCI bus designs use the EPM9320GC280-15 to consolidate scattered 74xx glue logic into a single programmable device. The 164 I/O pins handle all 16-bit ISA address, data, and control signals plus peripheral chip selects, while the 15 ns tPD complies with ISA's 120 ns bus cycle and PCI's 33 MHz timing budget. According to the MAX 9000 datasheet, each macrocell's programmable flip-flop with clear/preset supports registered chip-select behavior without external latches. Designers can drop a single EPM9320 into a socket on the motherboard to recover board space for additional memory or I/O.
推薦
DSP and Microprocessor Peripheral Controller
The EPM9320GC280-15 frequently sits between a DSP (such as TMS320C30 or ADSP-21xx) and its peripheral set, generating handshake and DMA control signals that would otherwise require a forest of TTL. With 320 macrocells and 117.6 MHz internal frequency, the device easily absorbs full peripheral state machines in a single chip. Its 5.0-V ISP via JTAG allows firmware revision updates without removing the part from the socket, a key benefit for field-deployed DSP boards. According to Altera's MAX 9000 application note AN-119, this glue-logic role typically uses 60-80% of macrocell capacity, leaving headroom for future feature additions.
推薦
Industrial Control State-Machine
The deterministic 15 ns timing and EEPROM non-volatility of the EPM9320GC280-15 make it ideal for industrial PLC, motor-control, and safety-interlock state machines that must power up in a known state without external boot memory. The 5 V tolerance and 4.75-5.25 V supply margin tolerate the noisy industrial bus environment where 24V transients couple into the logic supply. Its 280-pin CPGA package is socket-friendly, enabling field replacement without desoldering - a major advantage in factory-floor maintenance. Designers can implement 50-80 states with combinational outputs in a single EPM9320, replacing racks of relays and timers.
推薦
Telecom Backplane Control Logic
In telecom backplane applications, the EPM9320GC280-15 implements line-card interface controllers, alarm/status aggregation, and clock-distribution control where its 164 I/O pins and 320 macrocells drive dozens of low-speed control channels per line card. The deterministic 15 ns propagation delay ensures consistent framing across all line cards regardless of placement, critical for telecom timing budgets. Its JTAG boundary-scan support enables in-system interconnect testing per IEEE 1149.1, replacing expensive bed-of-nails fixtures. According to telecom industry case studies, consolidating backplane glue into a MAX 9000 reduces card BOM cost by 20-30%.
推薦
Legacy Industrial Motherboard Replacement
The EPM9320GC280-15 is commonly used to repair and sustain legacy 1990s-era industrial motherboards and VMEbus single-board computers where the original CPLD has failed and the surrounding through-hole assembly is otherwise intact. Its CPGA-280 package fits the original PGA socket without board modification, restoring full functionality at a fraction of full-board replacement cost. The 320-macrocell capacity matches or exceeds the original MAX 9000 design footprint, preserving any user-specific logic customization stored in the on-chip EEPROM. As of 2026-09-13, distributors like Jotrin and FPGAkey still stock the part specifically for these legacy-replacement programs.
推薦
推薦產品摘要
工程參考資料，適用於 EPM9320GC280-15 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM9320GC280-15N | EPM9320GC280-20 | EPM9320GC280-10 | EPM9320BC356-15 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-280 | CPGA-280 - same | CPGA-280 - same | CPGA-280 - same | BGA-356 - different package, same silicon |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns | 20 ns | 10 ns | 15 ns |
| Maximum Internal Frequency | 117.6 MHz | 117.6 MHz | 83.3 MHz | 125 MHz (typ) | 117.6 MHz |
| Maximum User I/O | 164 | 164 | 164 | 164 | 164 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Lead Finish | SnPb (standard) | Pb-free (matte Sn) | SnPb (standard) | SnPb (standard) | SnPb (standard) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主要差異化特點
- Same-package drop-in Pb-free variant (對比EPM9320GC280-15N)
- Pin-compatible speed-grade family (對比EPM9320GC280-10)
- Deterministic timing vs SRAM FPGAs (對比General SRAM FPGAs)
設計說明
The EPM9320GC280-15 requires 100 nF ceramic decoupling at every VCC pin and a single 10 uF bulk capacitor within 1 cm of the package. Estimated: at 117.6 MHz internal frequency with 50% logic toggle, ICC is approximately 200-300 mA typical per Altera MAX 9000 datasheet power tables. Use a star-ground topology from the CPGA socket back to the regulator to avoid ground bounce on JTAG signals.
The CPGA-280 package requires a through-hole PGA socket (e.g., 3M Textool or equivalent). Sockets extend the package height by approximately 6 mm above the PCB; allow clearance for top-side components and a heatsink if used. Because CPGA packages are not reflow-compatible, plan for socketed assembly and rework-friendly placement away from tall heatsinks. The missing-corner pin of the CPGA-280 keyed socket orients pin 1 for correct insertion.
Do not assume EPM9320GC280-15, EPM9320GC280-15N, EPM9320GC280-10, and EPM9320GC280-20 are interchangeable without checking timing - the speed grade affects fMAX and tPD. For 33 MHz PCI designs use only the -10 or -15 speed grade; the -20 violates PCI's 30 ns setup budget. The EPM9320BC356-15 is pin-incompatible despite sharing silicon - using it in a CPGA-280 socket will damage the part and the board.
Route JTAG signals TMS, TCK, TDI, TDO with 4.7 kohm pull-ups on TMS and TDI, and a 4.7 kohm pull-down on TCK as recommended in the MAX 9000 datasheet. Keep JTAG traces < 50 mm and avoid routing parallel to switching signals to preserve signal integrity. Provide a 4-pin 0.1-inch JTAG header or 1.27 mm tag-connect footprint for in-field ISP updates.
For high-fanout outputs (>24 mA), enable the EPM9320's slow slew-rate and ground-bounce control options in MAX+PLUS II to reduce simultaneous-switching noise on the 164 I/O bus. Estimated: with all 164 I/O toggling simultaneously, ground bounce can exceed 1 V if slew is not limited. Splitting registers across multiple LABs and using distributed clock trees (per Altera AN-119) reduces worst-case switching noise by approximately 30%.
合規資訊
Standard EPM9320GC280-15 uses SnPb lead finish (non-RoHS). For RoHS-compliant applications use the -N suffix variant. AEC-Q100 not applicable - this is a commercial-grade legacy part. ROHS3 compliance listed by fpgalink.com reflects current distributor data for the -15N variant.
