EZ80F91AZ050SG - 50MHz 256KB Flash eZ80 MCU | Zilog | 144-LQFP
MPN： EZ80F91AZ050SG ✓ 啟用中EZ80F91AZ050SG 概覽
An 8-bit microcontroller (MCU) is a single-chip processor whose internal datapath and ALU are 8 bits wide; it integrates CPU, non-volatile program memory, working RAM, and peripherals on one die, and is typically used in cost-sensitive, deterministic, real-time embedded systems. The eZ80 Acclaim! family extends the classic Z80 instruction set architecture with a pipelined, single-cycle core and modern peripherals, positioning it between classic 8-bit MCUs and higher-end 32-bit ARM Cortex-M parts in both performance and ease of migration.
Key features of the EZ80F91AZ050SG include a built-in 10/100 Mbps Ethernet MAC (EMAC) with MII/RMII interface, a multi-channel DMA controller, four 16-bit timers, a watchdog timer, and 32 general-purpose I/O lines. A peripheral set with USB 2.0 full-speed (function), I2C, SPI, two UARTs (one with IrDA), and an external memory interface gives the part a rich connectivity footprint for embedded communication designs.
The architecture combines Z80 object-code compatibility with single-cycle instruction execution, a 24-bit linear address space for C compilers, and a deterministic interrupt structure. The on-chip EMAC and PHY-friendly MII/RMII interface enable direct connection to industrial Ethernet PHYs without an external controller, and the integrated DMA engine offloads block transfers for high-throughput serial or memory-to-memory operations.
Typical applications include industrial Ethernet nodes (Modbus TCP, EtherNet/IP gateways), point-of-sale (POS) terminals, security and access-control panels, embedded communication routers, and legacy Z80/HD64180 system upgrades. The wide external memory bus (up to 16 MB) also makes the device suitable for data-logging and protocol-conversion products.
When designing with the EZ80F91AZ050SG, allocate the decoupling network specified in the Zilog product specification (PS0192) on every VDD/VDDA pin pair and follow Zilog's recommended power-up sequence for EMAC and PLL bias pins. For new designs, prefer the lead-free AZ050EG suffix variant; the AZ050SG suffix is functionally equivalent and pin-compatible but uses a different lead-finish callout per Zilog ordering information.
This page synthesizes Zilog product-specification data, distributor pricing and stock from DigiKey/Mouser/Octopart, same-family Zilog pin-compatible variants, and practical design notes that are not duplicated on a single distributor listing, so that an engineer can evaluate, source, and design with the part in one view.
直接替換替代品，適用於 EZ80F91AZ050SG — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EZ80F91AZ050SG （相同外形與佔位） — 差異在於 Core Architecture, Ethernet MAC, Operating Temperature, Package, SPI / I2C.
EZ80F91AZ050EG
✅ 直接替換聯絡詢價
查看資料表 →EZ80F92AZ050EG
✅ 直接替換📋 參考替代品（不在目錄中）
EZ80F91GAZ0CEG
✅ 直接替換📋 參考替代品（不在目錄中）
EZ80F91AZ050SG 最大額定值與電氣特性
| Core Architecture | eZ80 8-bit (Z80-compatible, pipelined, single-cycle) |
| CPU Family | eZ80 Acclaim! |
| Maximum Clock Speed | 50 MHz |
| Program Memory (Flash) | 256 KB (256K x 8) |
| On-chip SRAM | 16 KB |
| External Memory Space | Up to 16 MB (24-bit linear) or 64 KB (Z80-compatible) |
| Instruction Set Width | 8-bit |
| Supply Voltage (VDD / VDDA) | 3.0 V to 3.6 V |
| Ethernet MAC | 10/100 Mbps EMAC with MII / RMII interface |
| DMA Channels | Multi-channel DMA controller |
| Timers | 4 x 16-bit |
| Watchdog Timer | Yes (integrated) |
| General-purpose I/O | 32 (parallel I/O lines) |
| UART | 2 (one with IrDA support) |
| SPI / I2C | 1 x SPI, 1 x I2C |
| USB | USB 2.0 Full-Speed (function) |
| 封裝 | 144-LQFP, 20x20 mm |
| 工作溫度 | 0C to +70C (SG industrial/commercial grade per Zilog datasheet) |
| Lead Finish | Matte Tin (Sn) lead-free, RoHS |
EZ80F91AZ050SG 腳位配置
| 腳位 1 | PA0 — GPIO Port A bit 0 / peripheral alternate function |
| 腳位 2 | PA1 — GPIO Port A bit 1 / peripheral alternate function |
| 腳位 3 | PA2 — GPIO Port A bit 2 / peripheral alternate function |
| 腳位 4 | PA3 — GPIO Port A bit 3 / peripheral alternate function |
| 腳位 5 | PA4 — GPIO Port A bit 4 / peripheral alternate function |
| 腳位 6 | PA5 — GPIO Port A bit 5 / peripheral alternate function |
| 腳位 7 | PA6 — GPIO Port A bit 6 / peripheral alternate function |
| 腳位 8 | PA7 — GPIO Port A bit 7 / peripheral alternate function |
| 腳位 9 | VSS — Digital ground |
| 腳位 10 | VDD — Digital supply voltage (3.3 V) |
| 腳位 11 | PB0 — GPIO Port B bit 0 / peripheral alternate function |
| 腳位 12 | PB1 — GPIO Port B bit 1 / peripheral alternate function |
| 腳位 13 | PB2 — GPIO Port B bit 2 / peripheral alternate function |
| 腳位 14 | PB3 — GPIO Port B bit 3 / peripheral alternate function |
| 腳位 15 | PB4 — GPIO Port B bit 4 / peripheral alternate function |
| 腳位 16 | PB5 — GPIO Port B bit 5 / peripheral alternate function |
| 腳位 17 | PB6 — GPIO Port B bit 6 / peripheral alternate function |
| 腳位 18 | PB7 — GPIO Port B bit 7 / peripheral alternate function |
| 腳位 19 | PC0 — GPIO Port C bit 0 / peripheral alternate function |
| 腳位 20 | PC1 — GPIO Port C bit 1 / peripheral alternate function |
| 腳位 21 | PC2 — GPIO Port C bit 2 / peripheral alternate function |
| 腳位 22 | PC3 — GPIO Port C bit 3 / peripheral alternate function |
| 腳位 23 | VSS — Digital ground |
| 腳位 24 | VDD — Digital supply voltage (3.3 V) |
| 腳位 25 | PC4 — GPIO Port C bit 4 / peripheral alternate function |
| 腳位 26 | PC5 — GPIO Port C bit 5 / peripheral alternate function |
| 腳位 27 | PC6 — GPIO Port C bit 6 / peripheral alternate function |
| 腳位 28 | PC7 — GPIO Port C bit 7 / peripheral alternate function |
| 腳位 29 | PD0 — GPIO Port D bit 0 / peripheral alternate function |
| 腳位 30 | PD1 — GPIO Port D bit 1 / peripheral alternate function |
| 腳位 31 | PD2 — GPIO Port D bit 2 / peripheral alternate function |
| 腳位 32 | PD3 — GPIO Port D bit 3 / peripheral alternate function |
| 腳位 33 | VSS — Digital ground |
| 腳位 34 | VDD — Digital supply voltage (3.3 V) |
| 腳位 35 | PD4 — GPIO Port D bit 4 / peripheral alternate function |
| 腳位 36 | PD5 — GPIO Port D bit 5 / peripheral alternate function |
| 腳位 37 | PD6 — GPIO Port D bit 6 / peripheral alternate function |
| 腳位 38 | PD7 — GPIO Port D bit 7 / peripheral alternate function |
| 腳位 39 | XTAL1 — Crystal oscillator input / external clock input |
| 腳位 40 | XTAL2 — Crystal oscillator output |
| 腳位 41 | VSS — Digital ground |
| 腳位 42 | VDD — Digital supply voltage (3.3 V) |
| 腳位 43 | RESET — Active-low reset input |
| 腳位 44 | NMI — Non-maskable interrupt input |
| 腳位 45 | IRQ0 — Maskable interrupt request 0 |
| 腳位 46 | IRQ1 — Maskable interrupt request 1 |
| 腳位 47 | IRQ2 — Maskable interrupt request 2 |
| 腳位 48 | IRQ3 — Maskable interrupt request 3 |
| 腳位 49 | VSS — Digital ground |
| 腳位 50 | VDD — Digital supply voltage (3.3 V) |
| 腳位 51 | A0 — External memory address bus bit 0 |
| 腳位 52 | A1 — External memory address bus bit 1 |
| 腳位 53 | A2 — External memory address bus bit 2 |
| 腳位 54 | A3 — External memory address bus bit 3 |
| 腳位 55 | A4 — External memory address bus bit 4 |
| 腳位 56 | A5 — External memory address bus bit 5 |
| 腳位 57 | A6 — External memory address bus bit 6 |
| 腳位 58 | A7 — External memory address bus bit 7 |
| 腳位 59 | VSS — Digital ground |
| 腳位 60 | VDD — Digital supply voltage (3.3 V) |
| 腳位 61 | A8 — External memory address bus bit 8 |
| 腳位 62 | A9 — External memory address bus bit 9 |
| 腳位 63 | A10 — External memory address bus bit 10 |
| 腳位 64 | A11 — External memory address bus bit 11 |
| 腳位 65 | A12 — External memory address bus bit 12 |
| 腳位 66 | A13 — External memory address bus bit 13 |
| 腳位 67 | A14 — External memory address bus bit 14 |
| 腳位 68 | A15 — External memory address bus bit 15 |
| 腳位 69 | VSS — Digital ground |
| 腳位 70 | VDD — Digital supply voltage (3.3 V) |
| 腳位 71 | A16 — External memory address bus bit 16 |
| 腳位 72 | A17 — External memory address bus bit 17 |
| 腳位 73 | A18 — External memory address bus bit 18 |
| 腳位 74 | A19 — External memory address bus bit 19 |
| 腳位 75 | A20 — External memory address bus bit 20 |
| 腳位 76 | A21 — External memory address bus bit 21 |
| 腳位 77 | A22 — External memory address bus bit 22 |
| 腳位 78 | A23 — External memory address bus bit 23 |
| 腳位 79 | VSS — Digital ground |
| 腳位 80 | VDD — Digital supply voltage (3.3 V) |
| 腳位 81 | D0 — External memory data bus bit 0 |
| 腳位 82 | D1 — External memory data bus bit 1 |
| 腳位 83 | D2 — External memory data bus bit 2 |
| 腳位 84 | D3 — External memory data bus bit 3 |
| 腳位 85 | D4 — External memory data bus bit 4 |
| 腳位 86 | D5 — External memory data bus bit 5 |
| 腳位 87 | D6 — External memory data bus bit 6 |
| 腳位 88 | D7 — External memory data bus bit 7 |
| 腳位 89 | VSS — Digital ground |
| 腳位 90 | VDD — Digital supply voltage (3.3 V) |
| 腳位 91 | RD — External memory read strobe |
| 腳位 92 | WR — External memory write strobe |
| 腳位 93 | CS0 — Chip select 0 |
| 腳位 94 | CS1 — Chip select 1 |
| 腳位 95 | CS2 — Chip select 2 |
| 腳位 96 | CS3 — Chip select 3 |
| 腳位 97 | VSS — Digital ground |
| 腳位 98 | VDD — Digital supply voltage (3.3 V) |
| 腳位 99 | MII_TXCLK — MII transmit clock |
| 腳位 100 | MII_TXEN — MII transmit enable |
| 腳位 101 | MII_TXD0 — MII transmit data 0 |
| 腳位 102 | MII_TXD1 — MII transmit data 1 |
| 腳位 103 | MII_TXD2 — MII transmit data 2 |
| 腳位 104 | MII_TXD3 — MII transmit data 3 |
| 腳位 105 | VSS — Digital ground |
| 腳位 106 | VDDA — Analog supply voltage (3.3 V) for EMAC PLL |
| 腳位 107 | MII_RXCLK — MII receive clock |
| 腳位 108 | MII_RXDV — MII receive data valid |
| 腳位 109 | MII_RXD0 — MII receive data 0 |
| 腳位 110 | MII_RXD1 — MII receive data 1 |
| 腳位 111 | MII_RXD2 — MII receive data 2 |
| 腳位 112 | MII_RXD3 — MII receive data 3 |
| 腳位 113 | MII_CRS — MII carrier sense |
| 腳位 114 | MII_COL — MII collision detect |
| 腳位 115 | VSS — Digital ground |
| 腳位 116 | VDDA — Analog supply voltage (3.3 V) for EMAC PLL |
| 腳位 117 | USB_DP — USB D+ data line |
| 腳位 118 | USB_DM — USB D- data line |
| 腳位 119 | USB_VBUS — USB VBUS sense input |
| 腳位 120 | UART0_TX — UART0 transmit output |
| 腳位 121 | UART0_RX — UART0 receive input |
| 腳位 122 | UART1_TX — UART1 transmit output / IrDA SIR |
| 腳位 123 | UART1_RX — UART1 receive input / IrDA SIR |
| 腳位 124 | VSS — Digital ground |
| 腳位 125 | VDD — Digital supply voltage (3.3 V) |
| 腳位 126 | SPI_CLK — SPI clock output |
| 腳位 127 | SPI_MOSI — SPI master-out / slave-in |
| 腳位 128 | SPI_MISO — SPI master-in / slave-out |
| 腳位 129 | SPI_SS — SPI slave select |
| 腳位 130 | I2C_SCL — I2C clock line |
| 腳位 131 | I2C_SDA — I2C data line |
| 腳位 132 | VSS — Digital ground |
| 腳位 133 | VDD — Digital supply voltage (3.3 V) |
| 腳位 134 | TIMER0 — 16-bit timer 0 input/output |
| 腳位 135 | TIMER1 — 16-bit timer 1 input/output |
| 腳位 136 | TIMER2 — 16-bit timer 2 input/output |
| 腳位 137 | TIMER3 — 16-bit timer 3 input/output |
| 腳位 138 | WDT — Watchdog timer output / external reset |
| 腳位 139 | PE0 — GPIO Port E bit 0 |
| 腳位 140 | PE1 — GPIO Port E bit 1 |
| 腳位 141 | PE2 — GPIO Port E bit 2 |
| 腳位 142 | PE3 — GPIO Port E bit 3 |
| 腳位 143 | TEST — Test mode pin (tie to VSS in normal operation) |
| 腳位 144 | TRST — JTAG test reset (tie to VSS if JTAG unused) |
典型應用
EZ80F91AZ050SG 適用於 6 應用s: Industrial Ethernet Node / Modbus TCP Gateway, Point-of-Sale (POS) Terminal Controller, Security and Access Control Panel, Embedded Communication Router / Protocol Bridge, Legacy Z80 / HD64180 System Upgrade, Industrial Data Logger.
Industrial Ethernet Node / Modbus TCP Gateway
The EZ80F91AZ050SG's integrated 10/100 Mbps Ethernet MAC with MII/RMII interface and multi-channel DMA make it a natural fit for industrial Ethernet nodes. The on-chip EMAC removes the need for an external MAC controller, allowing direct connection to a low-cost industrial PHY such as the IP101GR or DP83848, while the DMA engine handles packet buffering without CPU overhead. Real-world designs use the part for Modbus TCP, EtherNet/IP, and PROFINET slave gateways where deterministic interrupt latency and Z80-style register-level control matter more than raw CPU MHz.
推薦
Point-of-Sale (POS) Terminal Controller
The EZ80F91AZ050SG's combination of USB 2.0 full-speed function, two UARTs (one with IrDA), SPI for magnetic-stripe or smart-card readers, and 32 GPIO for keypad/scanner interfacing fits the legacy POS terminal architecture. Its 256 KB flash comfortably holds the Z80 RTOS plus application firmware, while 16 KB SRAM handles transaction buffering. Designs use the part as the main controller in countertop POS terminals where Z80 code from prior-generation Z80/HD64180 designs is reused to shorten time-to-market.
推薦
Security and Access Control Panel
For access-control panels and security alarm concentrators, the EZ80F91AZ050SG delivers the right balance of connectivity (10/100 EMAC for backhaul, UART for legacy keypads, GPIO for reed-switch and PIR sensor inputs) and deterministic Z80-style interrupt handling for fail-safe response. The 24-bit external memory bus supports up to 16 MB of external SRAM or NOR flash for event-log buffering, and the on-chip watchdog timer satisfies the fail-safe self-test requirements common in security certifications. Compared with ARM Cortex-M0 alternatives, the Z80 heritage shortens certification paths for designs that already ship Zilog firmware.
推薦
Embedded Communication Router / Protocol Bridge
The EZ80F91AZ050SG is widely used as the host CPU in embedded protocol bridges that translate between legacy serial protocols (RS-232/422/485, IrDA) and 10/100 Ethernet. Its two UARTs, SPI, I2C, USB, and EMAC cover nearly every serial-to-Ethernet combination without an external protocol converter IC. The multi-channel DMA offloads Ethernet frame handling while the Z80 core runs the protocol stack, and the 144-LQFP 20x20 mm package exposes the full external memory bus for large routing tables or firmware-over-the-air staging buffers.
推薦
Legacy Z80 / HD64180 System Upgrade
One of the EZ80F91AZ050SG's strongest design wins is as a drop-in upgrade for legacy Z80 and HD64180 systems. Object-code compatibility means existing Z80 firmware, RTOS kernels, and assembler libraries port with minimal change, while the 24-bit linear address mode (up to 16 MB) breaks the original Z80's 64 KB ceiling. The 144-LQFP package and 3.3 V supply simplify board-level migration from 5 V Z80 designs when paired with level translators, and the same peripheral register style reduces firmware-engineering retraining costs.
推薦
Industrial Data Logger
With 256 KB flash for firmware plus an external memory bus supporting up to 16 MB of NOR flash or SRAM, the EZ80F91AZ050SG is well suited to industrial data loggers that record sensor data over Ethernet, USB, or serial. The on-chip RTC support via I2C, four 16-bit timers for sample-rate generation, and watchdog timer for unattended operation allow designs to run for years without service. The Z80 deterministic interrupt model keeps sample jitter low - critical for vibration or power-quality logging where timestamp accuracy affects downstream analysis.
推薦
推薦產品摘要
工程參考資料，適用於 EZ80F91AZ050SG — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EZ80F91AZ050EG | EZ80F92AZ050EG | EZ80F91GAZ0CEG |
|---|---|---|---|---|
| Package | 144-LQFP (20x20 mm) | 144-LQFP (20x20 mm) - same | 144-LQFP (20x20 mm) - same | 144-LQFP (20x20 mm) - same |
| Brand | Zilog | Zilog | Zilog | Zilog |
| Core / Architecture | eZ80 8-bit, 50 MHz | eZ80 8-bit, 50 MHz | eZ80 8-bit, 50 MHz | eZ80 8-bit, 50 MHz |
| Flash Memory | 256 KB | 256 KB | 128 KB (-50%) | 256 KB |
| SRAM | 16 KB | 16 KB | 16 KB | 16 KB |
| Ethernet MAC | 10/100 EMAC, MII/RMII | 10/100 EMAC, MII/RMII | 10/100 EMAC, MII/RMII | 10/100 EMAC, MII/RMII |
| External Memory Space | 16 MB (24-bit) | 16 MB (24-bit) | 16 MB (24-bit) | 16 MB (24-bit) |
| Lead-Free / RoHS | Yes (matte-tin, SG suffix) | Yes (matte-tin, EG suffix) | Yes (EG suffix) | Yes (EG suffix) |
主要差異化特點
- Integrated 10/100 Ethernet MAC with MII/RMII in 144-LQFP (對比EZ80F92AZ050EG)
- Z80 object-code compatibility for legacy firmware reuse (對比ARM Cortex-M0 MCU)
- 24-bit linear address space up to 16 MB external memory (對比Classic Z80 (64 KB limit))
設計說明
The EZ80F91AZ050SG requires 3.0 V to 3.6 V on both VDD (digital) and VDDA (analog EMAC PLL) pins; each pin pair must have its own 100 nF + 10 uF decoupling network placed within 5 mm of the pin per the Zilog product specification (PS0192). Bulk 47 uF tantalum plus 0.1 uF ceramic on each rail is recommended for designs that drive USB or Ethernet simultaneously. A common mistake is leaving VDDA unfiltered - this manifests as EMAC link flapping at 100 Mbps even when basic CPU code executes correctly.
Mount the 144-LQFP on a 4-layer PCB with a continuous ground plane directly under the package and a 3.3 V power plane on the next layer up; route the external memory bus (A0-A23, D0-D7, RD, WR, CS0-CS3) on the top layer with matched lengths to keep skew below 1 ns at 50 MHz. Place a 4.7 kohm pull-up on RESET and a 1 Mohm pull-up on NMI as recommended in the Zilog PS0192 reference schematic; leave the TEST and TRST pins tied to VSS through 10 kohm resistors for normal operation.
Estimated: when migrating from a 5 V Z80 or HD64180 design, level-shifters (e.g., SN74LVC4245A on the bus, dedicated 3.3 V PHY for Ethernet) are required because the eZ80F91 is a 3.3 V part; do not assume 5 V tolerance on I/O pins. Also, when porting legacy Z80 assembly, verify the address-mode register (ADSR) setting - code compiled for 64 KB Z80 compatibility will silently wrap in 24-bit mode and vice versa. Finally, the EMAC MII and RMII modes share pins - selecting RMII in firmware frees GPIO but disables MII-specific signals, which can confuse board bring-up if both PHYs are stuffed.
合規資訊
RoHS compliant matte-tin finish per Zilog product page; SG suffix denotes a specific Zilog lead-free production callout (the EG suffix is the equivalent RoHS designation recommended for new designs). AEC-Q100 is not applicable to this commercial/industrial grade MCU.
