TPS536C9T - Dual-Channel 12-Phase D-CAP+ Controller | TI
MPN： TPS536C9T ✓ 啟用中TPS536C9T 概覽
A multiphase buck controller is a power management IC that distributes a high-current step-down conversion across several interleaved phases, reducing input/output ripple, spreading thermal load, and improving transient response compared with a single-phase regulator. In the power management hierarchy, the TPS536C9T sits at the controller layer: it drives external smart power stages rather than integrating FETs, enabling server-class current levels far beyond what monolithic converters achieve.
Key features include the D-CAP+ control architecture for fast transient response, low output capacitance, and strong dynamic current sharing; native TLVR support for modern CPU load-transient profiles; an integrated non-volatile memory (NVM) for pin-free configuration; and compliance with the Intel VR14 SVID specification alongside a full PMBus interface for telemetry, fault management, and runtime adjustment.
Technically, the digital controller loops monitor per-phase current and temperature, and firmware-configurable parameters (stored in NVM) define phase count, switching behavior, and protection thresholds such as overcurrent, overvoltage, and overtemperature. The device is fully compatible with TI smart power stages (e.g., CSD95xxx family), simplifying design-in for multi-rail server and accelerator boards.
Typical applications include VR14-compliant CPU core power for servers and workstations, ASIC/FPGA accelerator rails, high-current point-of-load conversion in networking and datacenter equipment, and 12-phase TLVR evaluation platforms such as the TPS536C7EVM-051.
Design tip: because TLVR coupling and layout strongly affect transient performance, follow the TI layout guidelines for the SYNC/RESET and current-sense pins, and verify SVID boot sequencing against the platform's VR14 requirements.
直接替換替代品，適用於 TPS536C9T — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： TPS536C9T （相同外形與佔位） — 差異在於 Non-Volatile Memory, Package, Topology, Control Interface, Number of Channels.
TPS536C9RSLR
✅ 直接替換✗ 缺貨
$14.3182 / 單位
查看資料表 →TPS536C9RSLR
✅ 直接替換 ⚠️ 規格未經驗證✗ 缺貨
$14.3182 / 單位
查看資料表 →TPS536C9T 最大額定值與電氣特性
| 拓撲 | Step-down multiphase buck controller (D-CAP+) |
| 通道數 | 2 (N + M <= 12 phases total) |
| Maximum Total Output Current | 765 A (with smart power stages) |
| 輸入電壓範圍 | 4.5 V to 17 V |
| Output Voltage (minimum) | 0.25 V |
| Control Interface | PMBus, VR14 SVID |
| TLVR Support | Yes (trans-inductor voltage regulator) |
| Non-Volatile Memory | Built-in NVM configuration |
| Smart Power Stage Compatibility | TI smart power stages |
| 封裝 | 48-VFQFN (RSL), 6.00 mm x 6.00 mm, exposed pad |
| 安裝類型 | Surface Mount |
| Protection Features | OVP, OCP, OTP, fault management via PMBus |
| Telemetry | PMBus digital telemetry and monitoring |
| Applications Standard | Intel VR14 SVID compliant |
TPS536C9T 腳位配置
| 腳位 1 | VDD — Controller supply voltage [VERIFY: pin assignment per datasheet] |
| 腳位 19 | SYNC/RESET — Synchronization / reset function; connection guidance per TI E2E thread 1566151 |
| 腳位 - | PWMx — Phase PWM outputs to smart power stages (up to 12 phases) |
| 腳位 - | CSxP/CSxN — Per-phase current sense inputs |
| 腳位 - | SCL/SDA — PMBus clock and data |
| 腳位 - | SVID_ALERT/SVID_CLK/SVID_DATA — VR14 SVID interface signals |
| 腳位 - | VSEN/FB — Output voltage feedback sense |
| 腳位 - | GND — Ground / exposed pad thermal connection |
典型應用
TPS536C9T 適用於 6 應用s: Server CPU Core Power (VR14), TLVR Evaluation and Transient Testing, ASIC and FPGA Accelerator Cards, Networking and Datacenter Equipment, High-Current Point-of-Load Conversion, Industrial Compute and Edge Servers.
Server CPU Core Power (VR14)
The TPS536C9T is VR14 SVID compliant, making it a natural fit for Intel server and workstation CPU core rails. Its 4.5 V to 17 V input accepts the 12 V platform rail directly, and the N + M <= 12 phase D-CAP+ architecture with TLVR support delivers the multi-hundred-amp (up to 765 A) step loads CPUs present. The SVID interface lets the CPU command voltage setpoints and operating modes in real time, while PMBus telemetry reports per-rail voltage, current, and temperature for platform health monitoring. Using TI smart power stages, designers achieve low-BOM-cost dense layouts in the 6 mm x 6 mm controller footprint.
推薦
TLVR Evaluation and Transient Testing
For engineers characterizing 12-phase TLVR systems, the TPS536C9T pairs with electronic loads and load slammers to validate transient response, as discussed on TI's E2E forum for the TPS536C7EVM-051 platform. TLVR coupling enables extremely fast energy transfer during microsecond load steps, and the D-CAP+ controller modulates phase behavior to exploit this. The built-in NVM allows rapid reconfiguration of phase count and loop parameters without firmware host intervention. Designers should follow the datasheet layout guidance for SYNC/RESET and current-sense routing to get repeatable slammer test results.
推薦
ASIC and FPGA Accelerator Cards
AI accelerators and high-end FPGA cards require core rails from 0.25 V upward at hundreds of amps. The TPS536C9T supports outputs down to 0.25 V and up to 765 A total across two channels, with dynamic current sharing that balances thermal stress across power stages. For cards without an SVID-capable host, the PMBus interface provides full runtime voltage scaling, margining, and fault handling. The D-CAP+ loop's fast transient response reduces required output capacitance, freeing board area in dense accelerator form factors such as OCP and PCIe cards.
推薦
Networking and Datacenter Equipment
Switch, router, and storage systems use 12 V intermediate buses feeding multiple high-current point-of-load rails. The TPS536C9T's dual-channel architecture lets one controller serve two independent high-current rails (for example, ASIC core and SERDES/PHY rails), reducing controller count. PMBus telemetry integrates with shelf-management systems for predictive maintenance, and built-in NVM stores configuration without a host boot dependency. Its 4.5 V to 17 V input tolerance covers both 12 V and intermediate 5 V buses with margin, and protection features (OVP/OCP/OTP) support high-availability requirements.
推薦
High-Current Point-of-Load Conversion
Any design converting a 4.5 V to 17 V bus to a sub-1 V, multi-hundred-amp rail benefits from the TPS536C9T's multiphase approach, which interleaves phases to cancel ripple and spread heat. Compared with paralleled single-phase converters, D-CAP+ provides inherent current sharing and faster transient response with less output capacitance. Designers pair the controller with TI smart power stages that integrate driver and FETs, shortening design time and improving efficiency at the low duty cycles typical of 12 V-to-0.8 V conversion. The 48-pin QFN keeps controller footprint minimal on crowded POL areas.
推薦
Industrial Compute and Edge Servers
Rugged edge servers and industrial compute nodes running embedded CPUs still need VR14-class core power at reduced environmental budgets. The TPS536C9T's digital loop tolerates input variation across the 4.5 V to 17 V range from noisy industrial 12 V rails, and PMBus fault reporting supports remote diagnostics in unattended installations. NVM-stored configurations survive power cycles without host intervention, speeding brown-out recovery. Its SVID compliance covers embedded Intel processor families, and phase-count flexibility lets one controller design scale across product tiers from low to 12 phases.
推薦
推薦產品摘要
工程參考資料，適用於 TPS536C9T — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TPS536C9 | TPS536C9RSLR | TPS53622RSBT | ISL69269 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Renesas Electronics |
| Lifecycle Status | Active | Active | Active | Active | Active |
主要差異化特點
- TLVR topology support (對比TPS536C9)
- VR14 SVID compliance with PMBus (對比TPS53622RSBT)
- Built-in NVM configuration (對比ISL69269)
設計說明
Place the TPS536C9T close to the smart power stages and route each PWM output short and direct to minimize ringing. Per TI's datasheet layout section and E2E guidance, Kelvin-connect per-phase current sense (CSxP/CSxN) directly at the power stage sense points and keep the SYNC/RESET pin (pin 19) termination per datasheet recommendations. Use solid ground planes under the controller with the exposed pad soldered to a via-stitched thermal pad.
For TLVR designs, the auxiliary (ac-coupled) TLVR inductors and phase arrangement N+M strongly influence transient performance. D-CAP+ allows reduced output capacitance, but validate worst-case load steps (e.g., with an electronic load or load slammer) at maximum and minimum output voltage setpoints commanded over SVID. Confirm the smart power stage current ratings aggregate to your peak load with margin below the 765 A class ceiling.
NVM default configuration must match your phase assignment before first power-up - a mismatched phase map can trigger fault shutdowns. Also ensure SVID boot sequencing meets the platform's VR14 requirements: the CPU expects specific voltage presence before SVID handshake. If PMBus and SVID are both used, resolve interface arbitration in system firmware to avoid conflicting voltage commands.
合規資訊
Compliance details not present in provided web data; verify on TI product page quality section.
