TPS536C9TRSLR - Dual-Channel 12-Phase Buck Controller | TI
MPN: TPS536C9TRSLR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1 | $1.00 |
| 10 | $1 | $10.00 |
| 100 | $1 | $100.00 |
| 500 | $1 | $500.00 |
| 1,000 | $1 | $1,000.00 |
Drop-in alternatives for TPS536C9TRSLR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
TPS536C9RSLR
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →TPS53622RSBT
⚡ Same Package✓ In Stock
$3.96 / Unit
View Datasheet →TPS53624
⚡ Same Package✓ In Stock
$1.86 / Unit
View Datasheet →TPS53315
⚡ Same Package✓ In Stock
$3.52 / Unit
View Datasheet →TPS536C9TRSLR Maximum Ratings & Electrical Characteristics
| Topology | Multiphase buck (step-down) controller, D-CAP+ |
| Channels | 2 (N + M <= 12 phases, M <= 6) |
| Input Voltage Range | 4.5 V to 17 V |
| Output Voltage Range | 0.25 V to 5.5 V |
| Maximum Output Current | 765 A (total, system-dependent) |
| Control Interface | VR14 SVID + PMBus |
| TLVR Support | Yes, with LC open and short protection |
| Non-Volatile Memory | Yes (NVM configuration) |
| Power Stage Compatibility | TI NexFET smart power stages |
| Operating Temperature | -40C to +125C |
| Package | 48-VFQFN Exposed Pad (RSL) |
| Mounting Type | Surface Mount |
| Output Type | Positive, Adjustable |
| RoHS Status | Compliant |
| Function | Voltage Regulators - DC DC Switching Controller |
TPS536C9TRSLR Pin Configuration
| Pin 1 | PVIN/VDD — [DATA_NEEDED: full pin map per datasheet] |
| Pin 19 | RESET# — Reset output, pull-up resistor recommended when no CPU present (per TI E2E guidance) |
| Pin 44 | TEMP/NTC — Temperature sensing pin for unused rail (per TI E2E guidance) |
| Pin 49 | PAD — Exposed thermal pad, connect to GND |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
TPS536C9TRSLR is suitable for 6 applications: Server CPU Core Power (VR14), AI Accelerator Power Delivery, Networking and Telecom Line Cards, FPGA and ASIC Point-of-Load, Storage and Datacenter Servers, Industrial High-Current Computing.
Server CPU Core Power (VR14)
The TPS536C9TRSLR is VR14 SVID compliant, making it a natural controller for Intel server CPU core rails. Its N+M <= 12 phase allocation and 765A capability support sub-1V core voltages with 0.25V minimum output, while the D-CAP+ architecture delivers fast transient response for high di/dt load steps during turbo transitions. Placed centrally with TI NexFET smart power stages around the socket, it provides per-phase current sharing and PMBus telemetry for datacenter power management.
Recommended
AI Accelerator Power Delivery
AI accelerator SoCs impose extreme load transients that the TPS536C9TRSLR handles via native TLVR topology support with LC open and short protection. TLVR inductor coupling enables faster energy transfer between phases, reducing output impedance at high frequency compared with conventional coupled or discrete inductor designs. With up to 12 phases at 0.25-5.5V output, the controller scales to multi-hundred-amp accelerator core rails while PMBus telemetry supports rack-level power monitoring and thermal management in dense GPU pods.
Recommended
Networking and Telecom Line Cards
Line-card processors and switch ASICs require compact, efficient point-of-load conversion from a 12V intermediate bus. The TPS536C9TRSLR accepts 4.5-17V input directly and splits its two channels between ASIC core and I/O rails, reducing BOM count. Built-in NVM stores configuration locally, allowing boot-time rail setup without an external microcontroller, while PMBus enables live margining and fault reporting across shelf-management networks in telecom equipment.
Recommended
FPGA and ASIC Point-of-Load
High-end FPGAs and ASICs require tightly regulated core rails with fast response to bursty workloads. The TPS536C9TRSLR D-CAP+ control uses an adaptive on-time architecture that responds within switching cycles, minimizing undershoot during sudden logic activation. The 0.25-5.5V adjustable output covers modern core, GT, and auxiliary rails, and dual-channel operation lets one controller power both core and SerDes rails, improving board density and shared thermal budget.
Recommended
Storage and Datacenter Servers
Storage controllers and datacenter server SoCs benefit from the TPS536C9TRSLR dual-channel flexibility: one high-phase-count channel for a core rail and a low-phase-count channel for memory or SoC rails. -40C to +125C operation supports thermally constrained chassis, and PMBus fault logging enables predictive maintenance. The 48-pin VQFN exposed-pad package provides low thermal impedance to the PCB, essential in airflow-limited 1U server designs.
Recommended
Industrial High-Current Computing
Industrial edge-computing and machine-vision platforms using high-current processors can adopt the TPS536C9TRSLR where its 4.5-17V input tolerates industrial 12V bus variation and its NVM preserves configuration across power cycles without host intervention. D-CAP+ current sharing keeps phase thermals balanced on unventilated boards, and the wide 0.25-5.5V output range supports both legacy 3.3V and modern sub-1V processor cores from a single controller.
Recommended
Recommended Products Summary
Engineering reference data for TPS536C9TRSLR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | TPS536C9RSLR | TPS53622RSBT | TPS53624 | TPS53315 |
|---|---|---|---|---|---|
| Package | 48-VQFN (RSL) Exposed Pad | 48-VQFN (RSL) - same | 48-VQFN (RSB) | 48-VQFN | 48-VQFN |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Input Voltage Range | 4.5 V to 17 V | 4.5 V to 17 V | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Output Voltage Range | 0.25 V to 5.5 V | 0.25 V to 5.5 V | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Phases (N+M) | 12 (M <= 6) | 12 (M <= 6) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| TLVR Support | Yes (native, with LC open/short protection) | No | No | No | No |
| SVID Interface | VR14 SVID | VR14 SVID | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| PMBus + NVM | Yes | Yes | Yes | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Native TLVR topology support (vs TPS536C9RSLR)
- VR14 SVID compliance (vs TPS53622RSBT)
- 12-phase dual-channel scalability (vs TPS53315)
Design Notes
Per TI E2E layout guidance for the TPS536C9T: keep at least 800 mil distance between the controller and all power stages, place controller and power stages on a common ground plane, and keep PWMx signal routing short and away from switch nodes. These practices reduce noise coupling into current-sense and feedback inputs, which is critical for accurate phase current sharing at 12-phase counts.
The controller requires external TI NexFET smart power stages. Size per-phase current so that N+M phase allocation keeps each stage within its thermal limits at peak load; total 765A capability assumes adequate stage selection and airflow. Use the PMBus interface to verify per-phase current balance during bring-up and adjust shunt or DCR sensing settings stored in NVM accordingly.
When no CPU is attached, TI E2E forum guidance indicates pin 19 (RESET#) should be tied to a pull-up resistor and pin 44 set to the temperature pin of the unused rail. Also enable TLVR LC open and short protection settings only when TLVR inductors are actually installed; mismatched configuration can trip false faults at startup.
Compliance Information
RoHS compliance per standard TI DigiKey listing; other compliance details from TI product page quality data.
