TPS74801DRCR - 1.5A Low-VIN LDO with Soft-Start | Texas Instruments
MPN： TPS74801DRCR ✓ 啟用中TPS74801DRCR 概覽
An LDO (Low-Dropout) linear regulator is a type of voltage regulator that maintains a stable output voltage even when the input voltage is very close to the output voltage. It is a subclass of linear regulators, which in turn are part of the broader voltage regulator family within power management ICs. LDOs are essential for providing clean, low-noise power rails to sensitive analog and digital circuits, especially in battery-powered and low-voltage systems.
Key features of the TPS74801DRCR include a low dropout voltage of 60 mV typical at 1.5 A (with VBIAS = 5 V), a power-good (PG) output for supply monitoring and sequencing, an enable (EN) pin with active-high logic, and programmable soft-start to control inrush current. The device also offers overcurrent and thermal protection, ensuring robust operation in demanding environments.
Technically, the TPS74801 uses a PMOS pass element with a separate bias supply, allowing ultra-low input voltage operation while maintaining low dropout. The programmable soft-start is implemented via an external capacitor on the SS pin, which sets the output slew rate during startup. This prevents output overshoot and limits inrush current with large capacitive loads, and the monotonic startup is designed for safely powering processors, FPGAs, and ASICs.
Typical applications include powering FPGAs, DSPs, and microcontrollers from low-voltage rails, as well as supplying clean voltages for audio and RF circuits. The low VIN capability makes it ideal for systems running from 1.8 V or 2.5 V rails, where traditional LDOs with higher minimum input voltages cannot operate. The PG output simplifies power sequencing in multi-rail systems.
When designing with the TPS74801DRCR, ensure the VBIAS pin is supplied between 2.7 V and 5.5 V and VIN does not exceed 5.5 V. Place input and output capacitors close to the pins, size the SS capacitor for the load capacitance, and provide adequate copper pour for thermal dissipation at high dropout.
直接替換替代品，適用於 TPS74801DRCR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： TPS74801DRCR （相同外形與佔位） — 差異在於 Enable Pin, Output Type, Package, Soft-Start.
TPS74801TDRCRQ1
✅ 直接替換📋 參考替代品（不在目錄中）
TPS74801DRCT
✅ 直接替換📋 參考替代品（不在目錄中）
TPS74801DRCR 最大額定值與電氣特性
| 輸出類型 | Adjustable |
| 輸出電壓範圍 | 0.8 V to 3.6 V |
| 最大輸出電流 | 1.5 A |
| 輸入電壓範圍 | 0.8 V to 5.5 V |
| Bias Voltage Range (VBIAS) | 2.7 V to 5.5 V |
| 壓降電壓 | 60 mV typical at 1.5 A, VBIAS = 5 V |
| 電源良好輸出 | Yes |
| 致能腳位 | Yes (active-high) |
| 軟啟動 | Programmable via SS pin, monotonic |
| Protection Features | Overcurrent, thermal shutdown |
| 封裝 | 10-VSON (3x3 mm) [DRC] |
| 安裝類型 | Surface Mount |
| RoHS 狀態 | Compliant |
TPS74801DRCR 腳位配置
| 腳位 1 | EN — Enable input, active high |
| 腳位 2 | SS — Soft-start programming capacitor |
| 腳位 3 | FB — Feedback for adjustable output |
| 腳位 4 | PG — Power good output (open drain) |
| 腳位 5 | GND — Ground |
| 腳位 6 | VBIAS — Bias supply input, 2.7 V to 5.5 V |
| 腳位 7 | IN — Input supply, 0.8 V to 5.5 V |
| 腳位 8 | OUT — Regulated output, 1.5 A |
| 腳位 9 | OUT — Regulated output (paralleled) |
| 腳位 10 | GND (Pad) — Thermal pad / ground connection |
典型應用
TPS74801DRCR 適用於 6 應用s: FPGA Core and I/O Power, DSP and Processor Power Supplies, Low-VIN Point-of-Load Regulation, ASIC and Noise-Sensitive Digital Load Power, Multi-Rail Power Sequencing Systems, Industrial and Test Equipment Supplies.
FPGA Core and I/O Power
The TPS74801DRCR's monotonic, programmable soft-start and power-good output make it well suited for FPGA core rails such as 1.0 V or 1.2 V at up to 1.5 A. Placed after a 5 V bias rail, the 60 mV typical dropout at full load minimizes power loss, while the PG signal can gate downstream rails or enable the next sequenced regulator, satisfying FPGA power-up requirements without external supervisor ICs.
推薦
DSP and Processor Power Supplies
The TPS74801DRCR powers DSP and MCU cores from low-voltage rails thanks to its 0.8 V minimum VIN. The programmable soft-start limits capacitive inrush current on the input source, and overcurrent plus thermal protection protect against faults. In TI E2E designs it is used with 5 V bias to regulate low core voltages; the power-good flag simplifies multi-rail sequencing in processor-centric boards.
推薦
Low-VIN Point-of-Load Regulation
With VIN as low as 0.8 V, the TPS74801DRCR regulates directly from 1.8 V or 2.5 V system rails where most LDOs cannot operate. The separate VBIAS (2.7 V to 5.5 V) drives the PMOS pass element, delivering 1.5 A with only 60 mV typical dropout. This enables high-efficiency post-regulation after switching converters with minimal headroom loss in distributed power architectures.
推薦
ASIC and Noise-Sensitive Digital Load Power
The TPS74801DRCR provides controlled, monotonic startup specifically designed for powering ASICs and processors safely. The SS pin capacitor sets the ramp rate to match ASIC inrush specifications, while the adjustable 0.8 V to 3.6 V range covers modern process-node core voltages. Linear regulation adds no switching ripple, keeping rail noise low for noise-sensitive high-speed digital and mixed-signal loads.
推薦
Multi-Rail Power Sequencing Systems
The active-high EN input and open-drain power-good output of the TPS74801DRCR allow cascade sequencing: one regulator's PG signal enables the next rail. This is essential for processors and FPGAs that mandate specific rail order. The 10-VSON (3x3 mm) package keeps the solution compact, and soft-start monotonicity guarantees voltage ramps never dip during sequencing-dependent startup.
推薦
Industrial and Test Equipment Supplies
In industrial and bench-instrument designs, the TPS74801DRCR supplies clean 1.5 A rails to analog front ends and logic. Overcurrent and thermal shutdown provide fault robustness in 24 V-instrument environments after an intermediate buck stage. Its wide 0.8 V to 5.5 V input accommodates varied intermediate buses, and the compact DRC package fits dense PCB instrumentation layouts.
推薦
推薦產品摘要
工程參考資料，適用於 TPS74801DRCR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | TPS74801TDRCRQ1 | TPS74801DRCT | TPS7A8300ARGRR | TPS7A9201DSKR |
|---|---|---|---|---|---|
| Package | 10-VSON (3x3 mm) DRC | 10-VSON (3x3 mm) DRC - same | 10-VSON (3x3 mm) DRC - same | VQFN-20 (RGW) - different | WSON-8 (DSK) - different |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Maximum Output Current | 1.5 A | 1.5 A | 1.5 A | 2 A | 2 A |
主要差異化特點
- Ultra-low 0.8 V minimum input voltage (對比TPS7A8300ARGRR)
- Monotonic programmable soft-start for ASIC/FPGA safety (對比TPS7A9201DSKR)
- Automotive same-die upgrade path (對比TPS74801TDRCRQ1)
設計說明
Always supply VBIAS with 2.7 V to 5.5 V even when VIN is very low; the bias rail drives the PMOS pass element gate and enables the 60 mV typical dropout at 1.5 A. A common pitfall is tying VBIAS to VIN when VIN is 1.8 V - the regulator will not meet dropout or current specs. Derive VBIAS from a 5 V rail or the upstream buck output when available.
Place a 10 uF ceramic input capacitor and at least 10 uF effective output ceramic capacitor within 2-3 mm of the IN and OUT pins. The VSON-10 exposed thermal pad must be soldered to a grounded copper pour with multiple vias - it is the primary thermal and ground path. Refer to the layout section of TI datasheet TPS74801 (SBVS070) for the recommended footprint.
Size the SS capacitor for your load capacitance: large FPGA/ASIC decoupling banks require a slower ramp to avoid inrush tripping overcurrent protection. Use 1% tolerance resistors on the FB divider to maintain output accuracy. Note the unusual pinout - TI E2E confirms no pin-to-pin alternates exist, so never assume footprint compatibility with other TI LDOs without checking the datasheet.
合規資訊
RoHS compliant and lead-free per TI product page and distributor listings. AEC-Q100 applies to the TPS74801TDRCRQ1 variant, not the standard TPS74801DRCR.
