EP1M350F780I5 vs EP1M350F780C8 对比

详细并排对比 EP1M350F780I5 出自 Altera 和 EP1M350F780C8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1M350F780I5 EP1M350F780C8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $178.00 $175.00
Device Family Altera Mercury (EP1M) Enhanced Configuration Device Altera APEX Mercury (EP1M)
功能 FPGA configuration PROM with integrated controller —
Storage Density Code 350 (high-density) —
Supported Configuration Schemes Passive Serial, Active Serial, Fast Passive Parallel —
Internal Architecture Configuration controller + flash memory array —
Programming Method In-system programmable via Altera Quartus / JTAG —
封装 780-ball FineLine BGA (F780) 780-ball FineLine BGA
Temperature Grade (suffix "I") Industrial —
Speed Grade 5 C8 (commercial, speed bin 8)
Target FPGA Compatibility Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs —
JTAG Support Yes (IEEE 1149.1 boundary scan) —
Cascade / Multi-FPGA Support Yes, supports daisy-chained multi-FPGA boot —
Read-Back Yes —
RoHS 状态 [DATA_NEEDED: RoHS status] unknown (legacy device)
Lead-Free [DATA_NEEDED: lead-free status] —
Typical Gates — 350,000
Maximum Logic Elements (LEs) — 12,160
Embedded RAM Blocks — 4 dual-port RAM blocks
工作温度 — 0C to +85C (commercial)
Supply Voltage (Core) — [DATA_NEEDED: core Vcc]
I/O Standards Supported — LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards)
Global Clock Networks — 8
Configuration Interface — IEEE 1532 / passive serial / JTAG
Maximum User I/O — [DATA_NEEDED: user I/O count]
In-System Programmability — Yes (ISP via JTAG)
安装类型 — Surface Mount (BGA)
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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