EP1M350F780I5 vs EP1M350F780C8 Comparison
Detailed side-by-side comparison of EP1M350F780I5 by Altera and EP1M350F780C8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndSpecification Comparison
| Parameter | EP1M350F780I5 | EP1M350F780C8 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $178.00 | $175.00 |
| Device Family | Altera Mercury (EP1M) Enhanced Configuration Device | Altera APEX Mercury (EP1M) |
| Function | FPGA configuration PROM with integrated controller | β |
| Storage Density Code | 350 (high-density) | β |
| Supported Configuration Schemes | Passive Serial, Active Serial, Fast Passive Parallel | β |
| Internal Architecture | Configuration controller + flash memory array | β |
| Programming Method | In-system programmable via Altera Quartus / JTAG | β |
| Package | 780-ball FineLine BGA (F780) | 780-ball FineLine BGA |
| Temperature Grade (suffix "I") | Industrial | β |
| Speed Grade | 5 | C8 (commercial, speed bin 8) |
| Target FPGA Compatibility | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs | β |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | β |
| Cascade / Multi-FPGA Support | Yes, supports daisy-chained multi-FPGA boot | β |
| Read-Back | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown (legacy device) |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Typical Gates | β | 350,000 |
| Maximum Logic Elements (LEs) | β | 12,160 |
| Embedded RAM Blocks | β | 4 dual-port RAM blocks |
| Operating Temperature | β | 0C to +85C (commercial) |
| Supply Voltage (Core) | β | [DATA_NEEDED: core Vcc] |
| I/O Standards Supported | β | LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards) |
| Global Clock Networks | β | 8 |
| Configuration Interface | β | IEEE 1532 / passive serial / JTAG |
| Maximum User I/O | β | [DATA_NEEDED: user I/O count] |
| In-System Programmability | β | Yes (ISP via JTAG) |
| Mounting Type | β | Surface Mount (BGA) |
| MSL Level | β | [DATA_NEEDED: MSL rating] |