EP2SGX130GF40C4NGB vs EP2SGX130GF40C4NES 对比

详细并排对比 EP2SGX130GF40C4NGB 出自 Intel 和 EP2SGX130GF40C4NES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。

Intel

EP2SGX130GF40C4NGB - Stratix II GX FPGA, 132K LEs, 6.6K LABs | Intel

EP2SGX130GF40C4NGB Obsolete

Intel

EP2SGX130GF40C4NES ⚠ 最后一次采购

参数	EP2SGX130GF40C4NGB	EP2SGX130GF40C4NES
品牌	Intel	Intel
分类	FPGA & CPLD	FPGA & CPLD
生命周期状态	Obsolete	最后采购期
库存状态	有库存	有库存
单价（USD）	$640.00	$1,380.00
Series	Stratix II GX	—
Family	Enhanced Configuration (EPC) Devices	Stratix II GX
Logic Elements	132,540	132,540
Logic Array Blocks (LABs)	6,627	—
User I/O Pins	734	734
封装	1508-ball FBGA (GF40)	—
Terminal Pitch	1.00 mm	—
Speed Grade	C4	C4 (speed grade -4)
Temperature Grade	Commercial (0C to 85C)	—
Transceivers	Up to 20 multi-gigabit transceivers	—
Max Transceiver Data Rate	6.375 Gbps	—
PLLs	8	—
On-chip Memory	TriMatrix memory (block RAM + distributed RAM)	—
DSP Blocks	Yes (embedded multipliers)	Yes (variable, see datasheet)
Configuration	Enhanced / EPC mode	—
RoHS 状态	[DATA_NEEDED: RoHS status]	—
Logic Blocks / ALMs	—	Approximately 53,000 ALMs
Process Technology	—	90 nm CMOS
Core Voltage	—	1.2 V
Maximum Transceiver Data Rate	—	6.375 Gbps
Transceiver Channels	—	Up to 20 (4 to 20, device-dependent)
Total Package Pins	—	1508 (FC-FBGA ball grid)
Package Code	—	GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency	—	Up to 717 MHz
Embedded Memory	—	Approximately 4.5 Mbits (TriMatrix)
PLL Blocks	—	8
安装类型	—	Surface Mount (flip-chip BGA)
Lead-Free / RoHS	—	Yes (LEAD FREE per datasheet family code)
MSL 等级	—	Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
工作温度	—	Commercial Extended (per N suffix)
JEDEC Standard Reference	—	MS-034AAU-1