EP610LI-15 vs EP610IDC-15 对比
详细并排对比 EP610LI-15 出自 Altera 和 EP610IDC-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610LI-15 | EP610IDC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $48.50 | $9.95 |
| Device Family | Classic EPLD EP610 | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Counter Frequency (fCNT) | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| 工作温度 | 0 C to +70 C (commercial, "I" grade) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable / OTP |
| 封装 | 24-pin ceramic DIP, side-brazed, windowed (DIP-24) | 24-pin CerDIP (ceramic DIP) |
| 引脚数量 | 24 | — |
| Programming Method | UV erase + EPROM programmer | — |
| Logic Blocks | AND/OR array, 16 output macrocells | — |
| I/O Standard | TTL/CMOS compatible | — |
| 输出类型 | 3-state | — |
| RoHS 状态 | Non-compliant (ceramic DIP, SnPb finish typical) | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Manufacturer (current) | Rochester Electronics (authorized Altera legacy distributor) | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| 安装类型 | — | Through-hole |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |