ADC12C080CISQ - 12-Bit 80MSPS Pipelined ADC | Texas Instruments
料号： ADC12C080CISQ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $16.5 | $16.50 |
| 10 | $14.85 | $148.50 |
| 100 | $13.2 | $1,320.00 |
| 500 | $11.74 | $5,870.00 |
| 1,000 | $10.42 | $10,420.00 |
| 2,500 | $9.78 | $24,450.00 |
ADC12C080CISQ 概述
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltage signals into discrete digital codes at a specified sample rate. The ADC12C080 is specifically a pipelined ADC, which uses a multi-stage architecture to achieve high sample rates (tens to hundreds of MSPS) at moderate resolution (10-14 bits). Pipelined ADCs occupy a key position in the data converter hierarchy: ADC -> pipelined ADC -> data converter -> mixed-signal IC -> semiconductor. They are widely used in communications, imaging, and instrumentation where speed is more critical than extreme precision.
Key features of the ADC12C080CISQ include a 1.0 GHz full-power input bandwidth that preserves signal integrity for wideband IF undersampling, an internal 1.0V reference that eliminates external reference components, a clock duty cycle stabilizer that maintains ADC performance over a wide range of input clock duty cycles, and an integrated sample-and-hold circuit. The device supports both CMOS-compatible digital outputs and operates across the industrial temperature range of -40C to +85C. The 32-pin WQFN package provides a small footprint suitable for portable and space-constrained designs.
Architecturally, the ADC12C080 uses a multi-stage pipelined converter core with proprietary error correction to achieve 12-bit linearity without laser trimming. The high-bandwidth front-end sample-and-hold and the duty cycle stabilizer combine to enable direct IF sampling at frequencies up to several hundred MHz, making the part well-suited for communications receiver IF digitisation.
Typical applications for the ADC12C080CISQ include IF sampling in software-defined radio (SDR) receivers, ultrasound imaging front-ends, portable instrumentation such as handheld oscilloscopes and digital multimeters, CCD imaging digitisation in industrial cameras, and baseband signal acquisition in communications test equipment. The wide input bandwidth makes it especially suitable for undersampling RF signals without requiring explicit down-conversion stages.
When designing with the ADC12C080CISQ, use a low-noise, low-jitter clock driver to feed the CLK input because aperture jitter directly impacts SNR at high input frequencies. The exposed thermal pad must be soldered to a sufficiently large ground copper pour to maintain the rated thermal performance.
This page synthesises distributor pricing, drop-in 32-WQFN alternatives, and practical pipelined-ADC design notes not aggregated in the manufacturer datasheet alone.
直接替换替代料： ADC12C080CISQ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC12C080CISQ （相同外形与封装尺寸） ——差异在于 Input Type, Package, Resolution, RoHS Status, Architecture.
快速对比工具——选择替代料号进行并排对比：
ADC12C080CISQE/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC12C080CISQ/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC14C080CISQ/NOPB
✅ 直接替换✓ 有现货
$15.2 / 个
查看数据手册 →ADC14DS080CISQ/NOPB
✅ 直接替换✓ 有现货
$20.85 / 个
查看数据手册 →ADC14DS105AISQ/NOPB
✅ 直接替换✓ 有现货
$25.11 / 个
查看数据手册 →ADC14DS105CISQE/NOPB
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →ADC12C080CISQ 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 1 |
| Sample Rate | 65 / 80 MSPS (selectable via clock rate) |
| Architecture | Pipelined |
| Full-Power Input Bandwidth | 1.0 GHz |
| Input Type | Single-ended analog input |
| 电源电压 | Single +3.0 V |
| Reference Type | Internal (no external reference required) |
| Sample-and-Hold | Internal, integrated |
| Digital Output Format | Parallel CMOS-compatible outputs |
| Clock Duty Cycle Stabilizer | Yes (integrated) |
| Power-Down Mode | Yes |
| Data Ready / Clock Output | Yes |
| 工作温度范围 | -40C to +85C (industrial) |
| 封装 | 32-pin WQFN (5x5 mm) with exposed thermal pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (per NOPB suffix family) |
ADC12C080CISQ 引脚配置
| 引脚 1 | VIN+ — Positive analog input |
| 引脚 2 | VIN- — Negative analog input (complementary) |
| 引脚 3 | AGND — Analog ground |
| 引脚 4 | VCM — Common-mode voltage bypass |
| 引脚 5 | REFT — Internal reference top bypass |
| 引脚 6 | REFB — Internal reference bottom bypass |
| 引脚 7 | REFOUT — Internal reference output |
| 引脚 8 | AVDD — Analog +3.0V supply |
| 引脚 9 | DRVDD — Digital output driver supply |
| 引脚 10 | DGND — Digital ground |
| 引脚 11 | CLK — Sample clock input |
| 引脚 12 | CLK_GND — Clock ground reference |
| 引脚 13 | PD — Power-down input (active high) |
| 引脚 14 | D11 — Data output bit 11 (MSB) |
| 引脚 15 | D10 — Data output bit 10 |
| 引脚 16 | D9 — Data output bit 9 |
| 引脚 17 | D8 — Data output bit 8 |
| 引脚 18 | D7 — Data output bit 7 |
| 引脚 19 | D6 — Data output bit 6 |
| 引脚 20 | D5 — Data output bit 5 |
| 引脚 21 | D4 — Data output bit 4 |
| 引脚 22 | D3 — Data output bit 3 |
| 引脚 23 | D2 — Data output bit 2 |
| 引脚 24 | D1 — Data output bit 1 |
| 引脚 25 | D0 — Data output bit 0 (LSB) |
| 引脚 26 | DR — Data ready / output clock |
| 引脚 27 | OF — Output format / overflow flag |
| 引脚 28 | NC — Not connected (per datasheet) |
| 引脚 29 | NC — Not connected (per datasheet) |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | NC — Not connected (per datasheet) |
| 引脚 32 | EP — Exposed thermal pad (must be soldered to AGND pour) |
典型应用
ADC12C080CISQ 适用于 6 应用s: IF Sampling in Software-Defined Radio (SDR), Ultrasound Imaging Front-End Digitisation, Portable Digital Oscilloscope and DMM, CCD Imaging and Industrial Camera Digitisation, Communications Test Equipment Signal Acquisition, Baseband Receiver in Wired Communications.
IF Sampling in Software-Defined Radio (SDR)
The ADC12C080CISQ's 1.0 GHz full-power input bandwidth and 80 MSPS sample rate make it a strong fit for software-defined radio IF-sampling chains. The integrated sample-and-hold preserves wideband signal integrity, allowing direct digitisation of intermediate-frequency signals up to several hundred MHz without an explicit down-conversion mixer. The clock duty cycle stabilizer maintains ENOB performance even with relaxed clock source duty cycles, which simplifies clock-tree design. Power consumption is moderate thanks to selectable 65 MSPS low-power operation. Typical SDR use cases include QAM demodulator front-ends, narrowband receiver digitisation, and adaptive filter reference designs.
推荐
Ultrasound Imaging Front-End Digitisation
Medical and industrial ultrasound receivers require analogue front-ends followed by high-speed ADCs that capture reflected pulse echoes with adequate fidelity. The ADC12C080CISQ provides 12-bit resolution and 80 MSPS sampling that matches typical 30-40 MHz ultrasound IF stages, while its wide input bandwidth suppresses harmonic aliasing. The internal reference and integrated sample-and-hold minimise analogue front-end complexity, lowering overall BOM for compact portable ultrasound carts. Combined with a low-noise LDO such as the TPS7A4701, the ADC12C080CISQ delivers clean, low-jitter digitisation suitable for B-mode image reconstruction.
推荐
Portable Digital Oscilloscope and DMM
Handheld oscilloscopes and digital multimeters digitise one or more input channels at real-time sample rates in the 50-200 MSPS range. The ADC12C080CISQ, with selectable 65/80 MSPS operation, fits the lower-speed channel of a dual-channel scope and the acquisition path of a high-end DMM. Its single +3.0 V supply simplifies battery-powered designs, and its power-down mode extends runtime when the meter is in standby. The integrated reference and sample-and-hold reduce the analogue chain, allowing compact PCB layouts in slim handheld enclosures operating across -40C to +85C industrial temperature.
推荐
CCD Imaging and Industrial Camera Digitisation
Line-scan and area-scan CCD cameras in industrial inspection systems require high-speed ADCs to convert analogue pixel data into digital codes. The ADC12C080CISQ, with its 80 MSPS rate and 1.0 GHz input bandwidth, comfortably digitises typical CCD pixel data rates after correlated double sampling. The 12-bit resolution preserves dynamic range for grayscale imaging, while the internal sample-and-hold settles quickly between pixel conversions. Designers pair this ADC with a low-noise front-end op-amp such as the OPA1612 to drive the input and an FPGA such as the XC6SLX9 for downstream image processing.
推荐
Communications Test Equipment Signal Acquisition
Baseband digitisation in vector signal analysers, spectrum analyser IF stages, and communications testers needs wideband ADCs with low aperture jitter. The ADC12C080CISQ's 1.0 GHz input bandwidth combined with a low-jitter clock source yields SNR suitable for 60-70 dB dynamic range measurements. The CMOS parallel output interface simplifies FPGA capture at 80 MHz, and the duty cycle stabilizer tolerates non-50% clocks from low-cost clock generators. Production test racks benefit from the part's industrial temperature rating and its single-supply simplicity, reducing rack PSU design overhead.
推荐
Baseband Receiver in Wired Communications
Cable modem termination systems, DSL line drivers, and baseband industrial fieldbus receivers all require high-speed ADC front-ends to capture multi-MHz modulated signals. The ADC12C080CISQ's 80 MSPS rate oversamples baseband signals up to 40 MHz bandwidth cleanly, providing margin for digital filtering and equalisation. Its CMOS outputs feed directly into FPGA baseband processing blocks such as the XC6SLX9 or XC7A25T. The exposed thermal pad on the 32-WQFN package supports continuous operation at full sample rate, important for line-card deployments operating at elevated ambient temperatures.
推荐
推荐产品汇总
工程参考数据： ADC12C080CISQ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC12C080CISQE/NOPB | ADC12C080CISQ/NOPB | ADC14C080CISQ/NOPB | ADC14DS080CISQ/NOPB | ADC14DS105AISQ/NOPB | ADC14DS105CISQE/NOPB |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-WQFN (5x5) | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same | 32-WQFN (5x5) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 14 bits | 14 bits | 14 bits | 14 bits |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 105 MSPS | 105 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 2 (dual) | 2 (dual) | 2 (dual) |
| Internal Reference | Yes | Yes | Yes | Yes (typical for family) | Yes (typical for family) | Yes (typical for family) | Yes (typical for family) |
| Supply Voltage | +3.0 V | +3.0 V | +3.0 V | +3.0 V (typical family) | +3.0 V (typical family) | +3.0 V (typical family) | +3.0 V (typical family) |
| Pin-to-Pin Compatible | Yes (reference design) | Yes_yes_diff_does | Yes | Yes (verified) | Yes (verified) | Yes (verified) | Yes (verified) |
关键差异点
- Selectable 65/80 MSPS low-power operating mode （对比 ADC14C080CISQ/NOPB)
- 1.0 GHz full-power input bandwidth with internal sample-and-hold （对比 ADC08832IMMX/NOPB)
- Integrated clock duty cycle stabilizer （对比 ADC0820CC/D (legacy 8-bit ADC))
设计说明
Estimated: with a 32-WQFN package having approximately 30 C/W thermal resistance (typical for the family), at 80 MSPS the ADC12C080CISQ dissipates roughly 250 mW, producing ~7.5C junction rise at 25C ambient. Solder the exposed thermal pad (pin 32) to a continuous AGND copper pour of at least 1 square inch with multiple thermal vias to a ground plane to keep the junction below the 85C industrial limit. Avoid routing digital output traces through the analog ground region to prevent digital switching noise from coupling into the analog input path.
Aperture jitter on the CLK input is the dominant SNR limit at high input frequencies for any pipelined ADC. Estimated: with 1.0 GHz full-power input bandwidth and a typical 0.5 ps RMS aperture jitter, SNR at 100 MHz input approaches the datasheet value. Use a low-jitter clock driver such as a clean crystal oscillator followed by a CMOS fanout buffer (e.g., LVC family), and route the clock trace as a 50-ohm microstrip with controlled impedance. Avoid sharing the clock net with digital output switching signals to minimise crosstalk.
The ADC12C080CISQ accepts a single +3.0 V supply, but it draws analog (AVDD) and digital driver (DRVDD) current separately. Bypass AVDD with a 10 uF tantalum or ceramic bulk plus a 0.1 uF ceramic placed within 5 mm of the AVDD pin. Place a similar network on DRVDD; do not share bypass capacitors between analog and digital rails. Keep the analog and digital grounds tied at a single point near the exposed thermal pad. Using a low-noise LDO such as TPS7A4701 downstream of the switching converter reduces supply ripple-induced SFDR degradation in sensitive IF-sampling applications.
合规信息
RoHS and lead-free compliance per the /NOPB suffix family designation. AEC-Q100 not applicable - this is a commercial/industrial-grade part. MSL rating not extracted from verified data.
