ADS5485IRGC25 - 16-Bit 200MSPS ADC, Buffered Inputs | TI
料号： ADS5485IRGC25 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $78.42 | $78.42 |
| 10 | $71.3 | $713.00 |
| 100 | $64.55 | $6,455.00 |
| 500 | $58.2 | $29,100.00 |
| 1,000 | $52.18 | $52,180.00 |
ADS5485IRGC25 概述
What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is an architecture that processes analog input samples through multiple cascaded low-resolution stages, each stage resolving a portion of the output code before passing the amplified residue to the next stage. This architecture delivers the best combination of speed (tens to hundreds of MSPS) and resolution (12-16 bit) for applications such as test-and-measurement instrumentation, software-defined radio, medical imaging, and radar signal chains. Pipelined ADCs sit within the broader hierarchy of data converter -> ADC -> high-speed ADC -> pipelined ADC -> signal chain IC.
Key features include 200 MSPS guaranteed sample rate, 16-bit resolution, internal input buffer to ease front-end driving, LVDS outputs for low-noise digital signaling, and outstanding spurious-free dynamic range (SFDR) at high input frequencies. The buffered input removes the need for an external high-bandwidth op-amp, simplifying the analog front-end and reducing BOM count.
The architecture uses a switched-capacitor input sampling network followed by multi-bit-per-stage pipelined conversion with proprietary calibration. The wide input bandwidth and high SFDR enable direct IF sampling of signals up to several hundred MHz, which is increasingly used in lieu of analog mixing stages.
Typical applications include high-end test and measurement, software-defined radio receivers, communications base-station digitizers, radar and lidar processing, and medical imaging front-ends such as ultrasound. The pin-compatibility with the slower ADS5484/3/2/1 (200/170/135/105/80 MSPS) lets designers reuse a single PCB layout across multiple product tiers.
When designing with this device, pay close attention to the analog input network: the buffered input presents a fixed input impedance and requires a specific RC network at AINP/AINM to set the input common-mode and bandwidth. Maintain a solid ground plane on the VQFN-EP pad for thermal dissipation, and route LVDS pairs with 100 ohm differential impedance and length matching.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： ADS5485IRGC25 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADS5485IRGC25 （相同外形与封装尺寸） ——差异在于 Input Type, Package, Analog Supply Voltage, Number of Channels, Sample Rate.
快速对比工具——选择替代料号进行并排对比：
ADS5484IRGC25
✅ 直接替换✓ 有现货
$52.1 / 个
查看数据手册 →ADS5483IRGC25
✅ 直接替换📋 参考替代料（不在目录中）
ADS5482IRGC25
✅ 直接替换📋 参考替代料（不在目录中）
ADS5481IRGC25
✅ 直接替换✓ 有现货
$49.85 / 个
查看数据手册 →ADS62P48IRGC25
✅ 直接替换✓ 有现货
$49.2 / 个
查看数据手册 →ADS42JB69IRGC25
✅ 直接替换✓ 有现货
$53.4 / 个
查看数据手册 →ADS5485IRGC25 最大额定值与电气特性
| 分辨率 | 16 bit |
| Sample Rate | 200 MSPS (max) |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Type | Buffered (differential) |
| Analog Supply Voltage | 5 V (nominal) |
| Digital Supply Voltage | 3.3 V (nominal) |
| Output Interface | LVDS, parallel |
| 工作温度 | -40 C to +85 C (industrial) |
| 封装 | 64-pin VQFN (RGC) 9x9 mm with EP |
| 安装类型 | Surface Mount |
| MSL 等级 | 3 (per JEDEC J-STD-020) |
| RoHS 状态 | Compliant |
| Family Pin Compatibility | ADS5481/82/83/84/85 (80-200 MSPS) |
ADS5485IRGC25 引脚配置
| 引脚 1 | AVDD — Analog 5V supply |
| 引脚 2 | AVDD — Analog 5V supply |
| 引脚 3 | GND — Analog ground |
| 引脚 4 | AINP — Differential analog input positive (buffered) |
| 引脚 5 | AINM — Differential analog input negative (buffered) |
| 引脚 6 | VCM — Common-mode voltage output |
| 引脚 7 | GND — Analog ground |
| 引脚 8 | AVDD — Analog 5V supply |
| 引脚 9 | CLKP — Differential clock input positive |
| 引脚 10 | CLKM — Differential clock input negative |
| 引脚 11 | GND — Clock ground |
| 引脚 12 | DVDD — Digital 3.3V supply |
| 引脚 13 | DRVDD — Digital output driver 3.3V supply |
| 引脚 14 | DGND — Digital ground |
| 引脚 15 | D0_P — LVDS data output bit 0 positive |
| 引脚 16 | D0_M — LVDS data output bit 0 negative |
| 引脚 17 | D1_P — LVDS data output bit 1 positive |
| 引脚 18 | D1_M — LVDS data output bit 1 negative |
| 引脚 19 | D2_P — LVDS data output bit 2 positive |
| 引脚 20 | D2_M — LVDS data output bit 2 negative |
| 引脚 21 | D3_P — LVDS data output bit 3 positive |
| 引脚 22 | D3_M — LVDS data output bit 3 negative |
| 引脚 23 | D4_P — LVDS data output bit 4 positive |
| 引脚 24 | D4_M — LVDS data output bit 4 negative |
| 引脚 25 | D5_P — LVDS data output bit 5 positive |
| 引脚 26 | D5_M — LVDS data output bit 5 negative |
| 引脚 27 | D6_P — LVDS data output bit 6 positive |
| 引脚 28 | D6_M — LVDS data output bit 6 negative |
| 引脚 29 | D7_P — LVDS data output bit 7 positive |
| 引脚 30 | D7_M — LVDS data output bit 7 negative |
| 引脚 31 | D8_P — LVDS data output bit 8 positive |
| 引脚 32 | D8_M — LVDS data output bit 8 negative |
| 引脚 33 | D9_P — LVDS data output bit 9 positive |
| 引脚 34 | D9_M — LVDS data output bit 9 negative |
| 引脚 35 | D10_P — LVDS data output bit 10 positive |
| 引脚 36 | D10_M — LVDS data output bit 10 negative |
| 引脚 37 | D11_P — LVDS data output bit 11 positive |
| 引脚 38 | D11_M — LVDS data output bit 11 negative |
| 引脚 39 | D12_P — LVDS data output bit 12 positive |
| 引脚 40 | D12_M — LVDS data output bit 12 negative |
| 引脚 41 | D13_P — LVDS data output bit 13 positive |
| 引脚 42 | D13_M — LVDS data output bit 13 negative |
| 引脚 43 | D14_P — LVDS data output bit 14 positive |
| 引脚 44 | D14_M — LVDS data output bit 14 negative |
| 引脚 45 | D15_P — LVDS data output bit 15 positive |
| 引脚 46 | D15_M — LVDS data output bit 15 negative |
| 引脚 47 | DRC_P — LVDS data ready clock positive |
| 引脚 48 | DRC_M — LVDS data ready clock negative |
| 引脚 49 | OVR_P — LVDS over-range indicator positive |
| 引脚 50 | OVR_M — LVDS over-range indicator negative |
| 引脚 51 | RESET — Active-low reset (or power-down) |
| 引脚 52 | PDN — Active-low power-down |
| 引脚 53 | SEN — Serial interface enable |
| 引脚 54 | SCLK — Serial interface clock |
| 引脚 55 | SDATA — Serial interface data |
| 引脚 56 | SDOUT — Serial interface data out |
| 引脚 57 | MODE — Operating mode select |
| 引脚 58 | AVDD — Analog 5V supply |
| 引脚 59 | GND — Analog ground |
| 引脚 60 | AVDD — Analog 5V supply |
| 引脚 61 | GND — Analog ground |
| 引脚 62 | DVDD — Digital 3.3V supply |
| 引脚 63 | DGND — Digital ground |
| 引脚 64 | BIAS — Bias pin (external decoupling) |
典型应用
ADS5485IRGC25 适用于 6 应用s: Test & Measurement Instrumentation, Software Defined Radio (SDR), Communications Base Station Digitizer, Radar & Lidar Signal Processing, Medical Ultrasound Imaging, Industrial Data Acquisition.
Test & Measurement Instrumentation
The ADS5485IRGC25 suits wide-bandwidth oscilloscope and spectrum-analyzer front-ends where 16-bit resolution and 200 MSPS sample rate enable direct digitization of signals up to ~100 MHz without aliasing. Its buffered differential input simplifies the analog front-end by eliminating the need for an external high-bandwidth op-amp, reducing BOM and layout complexity. The LVDS parallel output keeps digital switching noise low, which is critical when capturing small analog signals. Designers using this part in digitizers benefit from the high SFDR at high input frequencies, allowing accurate capture of multi-tone test waveforms without spurious artifacts. Compared with slower ADCs, the 200 MSPS rate provides oversampling headroom for digital down-conversion.
推荐
Software Defined Radio (SDR)
The ADS5485IRGC25's 16-bit resolution and 200 MSPS sample rate make it well suited to SDR receivers that digitize intermediate-frequency (IF) signals up to several hundred MHz directly, replacing analog mixing stages. The buffered input handles the wide-bandwidth IF signals from RF front-ends, while the LVDS outputs keep digital emissions low to avoid coupling back into the RF chain. The pin-compatible ADS548x family allows designers to offer 80/105/135/170/200 MSPS variants on a single PCB layout, addressing different market tiers. Compared with a 14-bit alternative, the extra 2 bits of resolution translate directly into a larger dynamic range for capturing weak signals alongside strong interferers.
推荐
Communications Base Station Digitizer
The ADS5485IRGC25 is suitable for digitizing the IF outputs of multi-carrier GSM/UMTS/LTE base-station receivers, where 16-bit linearity and high SFDR are required to resolve small carriers in the presence of large blocking signals. The 200 MSPS rate supports wide observation bandwidths suitable for multi-channel carrier aggregation receivers. The buffered differential inputs ease PCB routing by accepting single-ended-to-differential conversion upstream without loading the ADC sample-and-hold. Compared with lower-speed ADCs, this part provides the oversampling margin needed for digital filtering and decimation in the FPGA or DSP downstream. The 5 V analog / 3.3 V digital supplies are common in telecom hardware, simplifying power-tree design.
推荐
Radar & Lidar Signal Processing
The ADS5485IRGC25's 200 MSPS sample rate and 16-bit resolution support wide-bandwidth radar return digitization in ground-based and airborne radar front-ends, including synthetic aperture radar (SAR) and phased-array receivers. The buffered differential input allows direct connection to a low-noise amplifier or filter network without external buffers, simplifying the analog chain. The high SFDR preserves the dynamic range needed to detect small targets in the presence of clutter and large nearby returns. Compared with 12 or 14-bit ADCs, the 16-bit core provides the additional dynamic range required for high-clutter environments, while the LVDS outputs minimize digital coupling into the RF front-end.
推荐
Medical Ultrasound Imaging
The ADS5485IRGC25 enables digital beamforming in mid-to-high-end ultrasound systems where each channel must digitize RF signals up to ~50-100 MHz with high dynamic range. The 16-bit resolution and high SFDR allow detection of small echoes from deep tissue without saturating on large surface reflections. The buffered input simplifies the front-end by accepting the output of the time-gain-compensation (TGC) amplifier directly, and the LVDS outputs transport data to the beamformer FPGA with minimal EMI. The pin-compatible family lets designers reuse a single PCB for 16-channel modules that span a range of probe-center frequencies. The 5 V/3.3 V supplies are easy to derive from the isolated medical-grade power rails typical in ultrasound carts.
推荐
Industrial Data Acquisition
The ADS5485IRGC25 fits high-channel-count industrial data-acquisition systems such as vibration monitoring on rotating machinery, where the 200 MSPS rate captures fast transient signatures while the 16-bit resolution preserves amplitude accuracy for spectral analysis. The buffered input accommodates the long cable runs and varied source impedances typical of industrial sensor networks. Industrial temperature grade (-40C to +85C) matches the harsher environments of factory floors, motor-control cabinets, and outdoor enclosures. Compared with audio-bandwidth ADCs, the 200 MSPS rate provides massive oversampling that lets DSP algorithms implement sharp anti-alias filters and high-resolution FFT analysis. The LVDS outputs keep emissions low in electrically noisy industrial settings.
推荐
推荐产品汇总
工程参考数据： ADS5485IRGC25 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADS5484IRGC25 | ADS5483IRGC25 | ADS5482IRGC25 | ADS5481IRGC25 | ADS62P48IRGC25 | ADS42JB69IRGC25 |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 14 bit | 16 bit |
| Sample Rate (max) | 200 MSPS | 170 MSPS | 135 MSPS | 105 MSPS | 80 MSPS | 210 MSPS | 250 MSPS |
| Output Interface | LVDS, parallel | LVDS, parallel | LVDS, parallel | LVDS, parallel | LVDS, parallel | LVDS, parallel | JESD204B |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V | 3.3 V | 1.8 V / 3.3 V |
| Input Type | Buffered differential | Buffered differential | Buffered differential | Buffered differential | Buffered differential | Buffered differential | Buffered differential |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Pin-Compatible Upgrade Path | This part | Down-grade to 170 MSPS | Down-grade to 135 MSPS | Down-grade to 105 MSPS | Down-grade to 80 MSPS | Down-grade to 14-bit, 210 MSPS | Upgrade to 250 MSPS, JESD204B (interface change) |
关键差异点
- Highest sample rate in the pin-compatible ADS548x family （对比 ADS5484IRGC25)
- 16-bit resolution vs lower-bit alternatives （对比 ADS62P48IRGC25)
- LVDS parallel output preserves classic interface compatibility （对比 ADS42JB69IRGC25)
设计说明
Use a star-ground topology with separate analog and digital ground planes joined only at the ADC's AGND/DGND pins. Place the analog input RC network (typically 50 ohm series, 10 pF differential) within 5 mm of the AINP/AINM pins to limit common-mode kickback from the internal input buffer and preserve SFDR at high input frequencies.
Route the LVDS data pairs (D0..D15) and DRC clock over 100 ohm differential microstrip with intra-pair length matching of better than 1 mm. Keep total length under 150 mm to avoid excessive ISI at 200 MSPS. Use series 100 ohm termination at the FPGA/ASIC end, not at the ADC end, to prevent reflections.
Decouple AVDD with a 10 uF bulk plus 100 nF and 10 nF ceramics placed as close as possible to each AVDD pin. DVDD and DRVDD require similar treatment; do not share decoupling capacitors between analog and digital rails. A ferrite bead between AVDD and DRVDD planes helps isolate digital switching noise from the analog front-end.
The VQFN-64 (RGC) 9x9 mm package exposes the thermal pad (pin 65, not numbered on the package outline) which must be soldered to a continuous ground plane with at least 16 thermal vias on a 1.2 mm pitch. This achieves the datasheet thermal resistance and prevents the die from exceeding 125 C junction temperature at the maximum sample rate and full-scale input.
Do not operate the ADS5485IRGC25 above 200 MSPS; the family is pin-compatible but the 170/135/105/80 MSPS parts will not function correctly at 200 MSPS and may produce degraded SFDR. Always check the speed-grade suffix and the speed-grade register value after reset to confirm the device initialized correctly before starting data acquisition.
合规信息
RoHS compliant per TI product page (verified Oct 2026). Industrial temperature grade, not automotive qualified - no AEC-Q100 variants in the ADS5485 family. MSL Level 3 per JEDEC J-STD-020.
