EPM7096LC84-10 - 96-Macrocell MAX 7000 CPLD, 10ns, 84-PLCC | Intel
料号： EPM7096LC84-10 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.8 | $9.80 |
| 10 | $8.65 | $86.50 |
| 100 | $7.4 | $740.00 |
| 500 | $6.2 | $3,100.00 |
| 1,000 | $5.1 | $5,100.00 |
EPM7096LC84-10 概述
A Complex Programmable Logic Device (CPLD) is a non-volatile, reprogrammable digital integrated circuit that sits hierarchically between simple SPLDs/GALs and full FPGAs. Within the broader taxonomy, CPLDs fall under programmable logic devices (PLDs), which sit under digital logic ICs, which in turn belong to the integrated circuit (semiconductor) family. CPLDs are valued for their deterministic timing, instant-on EEPROM configuration, and predictable I/O behavior, making them well suited to glue-logic, bus-interface, and control-plane tasks in mixed-signal systems.
The EPM7096LC84-10 features 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. It supports MultiVolt I/O for interfacing with 2.5-V, 3.3-V, and 5.0-V logic on the same die, and provides programmable macrocell flip-flops with selectable D, T, JK, or SR operation. The shared programmable interconnect array (PIA) routes signals between LABs, and each macrocell includes a product-term-based logic array, a programmable register, and a tri-state output buffer for bidirectional I/O.
Typical applications of the EPM7096LC84-10 include address decoding and bus-interface glue logic in 5-V microcontrollers and DSP systems, peripheral control for printers and legacy industrial controllers, state-machine-driven I/O expansion, JTAG-boundary-scan test access, and replacement of multiple discrete 74LS/74HC TTL gates to reduce board area. Because the MAX 7000 uses EEPROM cells, designs retain their configuration through power cycles with no external boot PROM.
When designing with this device, ensure that VCC stays within the 4.75 V to 5.25 V commercial range, that JTAG signals TDI/TMS/TCK/TDO are pulled to a defined logic level when not in use, and that I/O rise/fall times are accounted for in timing closure - the shared PIA structure means worst-case tPD is identical for any internal path. For new designs, evaluate MAX II or MAX V modern low-power equivalents, which consume less quiescent current and offer smaller packages while maintaining 5-V tolerant I/O.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone - use it alongside the official MAX 7000 datasheet from Intel.
直接替换替代料： EPM7096LC84-10 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM7096LC84-10 （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Programming Interface, Family, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
EPM7096LC84-12
✅ 直接替换📋 参考替代料（不在目录中）
EPM7096LC84-15
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →EPM7128ELC84-15
✅ 直接替换📋 参考替代料（不在目录中）
EPM7128SLC84-10N
✅ 直接替换📋 参考替代料（不在目录中）
EPM7128ELC84-10
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPM7064LC84-10
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EPM7096LC84-10 最大额定值与电气特性
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 96 |
| Logic Array Blocks (LABs) | 4 |
| Maximum User I/O Pins | 36 |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) |
| 封装 | 84-PLCC (J-Lead) |
| Process Technology | EEPROM-based, 5.0 V low-power CMOS (L) |
| Supply Voltage (VCC) | 5.0 V nominal (4.75 V - 5.25 V) |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG |
| MultiVolt I/O | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface |
| 工作温度范围 | 0C to +70C (Commercial, 'C') |
| Configuration Memory | Non-volatile EEPROM (instant-on) |
| Programmable Interconnect | PIA (Programmable Interconnect Array) |
| 安装类型 | Surface Mount (PLCC socket or SMT) |
EPM7096LC84-10 引脚配置
| 引脚 1 | I/O — User I/O pin (macrocell-driven bidirectional) |
| 引脚 2 | I/O — User I/O pin |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | I/O — User I/O pin |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | I/O — User I/O pin |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | I/O — User I/O pin |
| 引脚 10 | I/O — User I/O pin |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin |
| 引脚 13 | I/O — User I/O pin |
| 引脚 14 | I/O — User I/O pin |
| 引脚 15 | I/O — User I/O pin |
| 引脚 16 | I/O — User I/O pin |
| 引脚 17 | I/O — User I/O pin |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | GND — Ground |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | I/O — User I/O pin |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | I/O — User I/O pin |
| 引脚 29 | I/O — User I/O pin |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | I/O — User I/O pin |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | GND — Ground |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | TDI — JTAG Test Data In |
| 引脚 44 | TMS — JTAG Test Mode Select |
| 引脚 45 | TCK — JTAG Test Clock |
| 引脚 46 | TDO — JTAG Test Data Out |
| 引脚 47 | I/O — User I/O pin |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | I/O — User I/O pin |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | GND — Ground |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | I/O — User I/O pin |
| 引脚 61 | I/O — User I/O pin |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | GND — Ground |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | I/O — User I/O pin |
| 引脚 78 | I/O — User I/O pin |
| 引脚 79 | I/O — User I/O pin |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | GND — Ground |
| 引脚 84 | VCC — +5 V supply |
典型应用
EPM7096LC84-10 适用于 6 应用s: 5V Microcontroller Glue Logic, Bus Interface & Address Decoding, Industrial Control & State Machines, Legacy Peripheral Control (Printers / Scanners), JTAG Boundary-Scan Test Access, Replacement of Discrete TTL Gate Arrays.
5V Microcontroller Glue Logic
The EPM7096LC84-10's 96 macrocells and 36 I/O pins make it well suited to replace chains of 74LS/74HC glue logic around a 5-V microcontroller such as the Intel 8051, Motorola 68HC11, or Microchip PIC. With a 10 ns tPD, the device can decode address lines and generate chip-select strobes at system clock rates up to 50 MHz without timing-margin concerns. Its 5.0-V MultiVolt I/O ports can directly drive 3.3-V peripherals through series resistors or level translators, simplifying mixed-voltage board designs. Designers should reserve JTAG pins TDI/TMS/TCK/TDO for boundary-scan access during board test, allowing in-system firmware updates without removing the chip.
推荐
Bus Interface & Address Decoding
The EPM7096LC84-10 is widely deployed in ISA, PCI, and proprietary backplane interfaces where address decoding must be deterministic across temperature. Its product-term-based logic array and shared PIA deliver fixed tPD independent of which LAB a signal enters, which is critical for chip-select timing in DMA-bus architectures. The 36 user I/O pins are sufficient to decode 24-bit address buses plus 8-chip-select outputs. The 5.0-V VCC rail aligns with legacy 5-V host bus signaling, eliminating level-translation circuitry. For modern 3.3-V-only systems, the same die is offered in 3.3-V variants (EPM7096S) that retain pinout compatibility.
推荐
Industrial Control & State Machines
The non-volatile EEPROM configuration of the EPM7096LC84-10 makes it ideal for industrial PLCs and motor-control boards that must boot into a known state without external boot PROMs. Each of the 96 macrocells can implement D, T, JK, or SR flip-flops, supporting large Moore or Mealy state machines for sequencing conveyor belts, solenoid drivers, or stepper-motor pulse generators. The 0C to +70C commercial operating range suits most factory-floor enclosures; industrial-temperature variants (EPM7096LI84-10) extend coverage to -40C to +85C. The JTAG ISP interface lets technicians re-load ladder-logic-equivalent state machines through the board's test connector without removing the chip.
推荐
Legacy Peripheral Control (Printers / Scanners)
Print engines, scanner stepper motors, and legacy USB-to-parallel bridges often require parallel-control glue logic that the EPM7096LC84-10 implements in a single chip. Its 36 I/O pins can drive head-position encoders, paper-feed stepper coils, and LED status banks simultaneously, while the macrocell array handles stepper pulse-train generation and PWM-like dimming control. The instant-on EEPROM configuration means the printer is operational within microseconds of power-up, satisfying warm-boot timing requirements. Replacement of original 74LS glue logic with one CPLD reduces PCB area and improves noise immunity through fewer high-speed signal traces.
推荐
JTAG Boundary-Scan Test Access
The built-in IEEE 1149.1 JTAG interface of the EPM7096LC84-10 lets the device itself act as a boundary-scan master or slave in board-level test fixtures. By assigning all 36 user I/O pins to JTAG boundary-scan registers, the CPLD can chain test access to adjacent BGA and QFP devices that lack visible test points. The 10 ns tPD does not limit boundary-scan capture-clock rates since scan operations occur at the JTAG TCK frequency (typically 10-100 MHz), independent of the CPLD's functional tPD. Combined with the ISP capability, the same JTAG port re-loads firmware and runs structural board tests - a true single-test-access design.
推荐
Replacement of Discrete TTL Gate Arrays
Designers often face legacy boards populated with 30+ discrete 74LS/74HC/74F packages implementing address decoding, bus arbitration, and interrupt prioritization. The EPM7096LC84-10, with 96 macrocells, can absorb all of these functions into a single 84-PLCC device, reducing PCB area, lowering power consumption through CMOS design, and improving reliability by removing solder joints. The MultiVolt I/O pins let the same CPLD interface to 5-V and 3.3-V logic islands on the board, eliminating the cross-voltage glue that often accompanies mixed-logic redesigns. Migration to the same-die MAX II EPM570 is recommended only if board area constraints demand a smaller package.
推荐
推荐产品汇总
工程参考数据： EPM7096LC84-10 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM7096LC84-12 | EPM7096LC84-15 | EPM7128ELC84-15 | EPM7128SLC84-10N | EPM7064LC84-10 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Macrocells | 96 | 96 | 96 | 128 | 128 | 64 |
| Propagation Delay (tPD) | 10 ns | 12 ns | 15 ns | 15 ns | 10 ns | 10 ns |
| Logic Array Blocks | 4 | 4 | 4 | 8 | 8 | 4 |
| Maximum User I/O | 36 | 36 | 36 | 36 | 36 | 36 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Pin-to-Pin Drop-In | Reference | Yes | Yes | Yes | Yes | Yes |
关键差异点
- Higher macrocell density at same speed grade （对比 EPM7064LC84-10)
- Faster speed grade than EPM7128ELC84-15 （对比 EPM7128ELC84-15)
- 5-V native supply matches legacy 5-V systems （对比 MAX II EPM570 (modern alternative))
设计说明
Estimated: At a 5.0 V VCC with all 36 I/O pins toggling at 25 MHz into 50 pF loads, the EPM7096LC84-10 draws approximately 200-300 mA. Place one 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin (pins 84, plus internal supply pins) and a 10 uF bulk tantalum or ceramic capacitor at the board's power-entry point. The four GND pins (11, 23, 41, 55, 69, 83) must all be tied to a low-impedance ground plane; missing even one GND connection can cause intermittent JTAG failures under load.
Route the four JTAG signals (TDI pin 43, TMS pin 44, TCK pin 45, TDO pin 46) as a short, impedance-controlled cluster with a guard ground on either side. Keep JTAG traces under 50 mm to avoid reflection-induced programming failures. The TCK line in particular should be length-matched to within 5 mm of any buffered JTAG node downstream. If the board uses a 10-pin or 14-pin JTAG header, add a 10 kohm pull-up on TMS and TDI per IEEE 1149.1 spec to keep the TAP controller in a benign state during board reset.
Do not assume the -10, -12, and -15 speed-grade variants are interchangeable without re-running timing closure. The 2 ns and 5 ns tPD differences can violate setup/hold margins in synchronous designs clocked above 33 MHz. Pinout is identical across speed grades, so PCB fabrication is unaffected - only the device marking changes. Also note that the 'L' suffix denotes the 5-V low-power CMOS process; the 3.3-V 'S' variants (EPM7096SLC84-10) require VCC of 3.3 V and are NOT pin-compatible at the supply pin - mixing them on the same board will damage the 'L' part.
合规信息
RoHS/lead-free status not stated in verified web data for this specific MPN. The MAX 7000 family is generally lead-bearing per legacy Altera process; the lead-free variant carries a '-N' suffix in the part number (e.g., EPM7096LC84-10N). Verify against the device marking or manufacturer PCN for production designs.