EPM7096LC84-7 - 96-Macrocell MAX 7000 CPLD, 7.5ns, PLCC-84 | Intel
料号： EPM7096LC84-7 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.4 | $2,740.00 |
| 500 | $22.9 | $11,450.00 |
| 1,000 | $19.85 | $19,850.00 |
EPM7096LC84-7 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits hierarchically between simple SPLDs/PALs and larger FPGAs in the programmable logic taxonomy: SPLD -> CPLD -> FPGA -> programmable logic -> digital IC. CPLDs are characterized by deterministic timing, instant-on behavior (no boot load), and on-chip non-volatile configuration memory, which makes them ideal for glue-logic, bus interfacing, and control applications where predictable timing and zero-boot-delay operation are required.
Key features of the EPM7096LC84-7 include 96 macrocells organized in 4 Logic Array Blocks (LABs), 64 user I/O pins, a 7.5 ns tPD (pin-to-pin logic delay) corresponding to the speed grade -7, and 5.0-V in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. The device operates from a single 5.0 V supply (VCCINT/VCCIO combined for the LC family) and supports commercial temperature ranges. Pin-compatibility across the MAX 7000 family allows migration between EPM7064, EPM7096, and higher densities within the same 84-pin PLCC footprint.
The MAX 7000 architecture is built on EEPROM non-volatile cells with a second-generation MAX architecture, providing five-pin programmable logic delays, programmable flip-flops with individual clear, preset, clock, and clock-enable controls, and a programmable interconnect array (PIA) that routes signals between LABs. This gives deterministic, simulation-matched timing for asynchronous state machines and address decoding.
Typical applications include bus address decoding, peripheral glue logic, interface bridging between microcontrollers and legacy peripherals, asynchronous state machines, and board-level reset/power-sequencing controllers in industrial, telecom, and embedded computing systems. The wide 5V tolerance and instant-on behavior are particularly valued in 5V legacy industrial backplanes.
When designing with this part, ensure the JTAG chain (TCK, TMS, TDI, TDO) is correctly terminated and that the I/O banks are powered simultaneously to avoid latch-up. The 7.5 ns speed grade is the slowest in the MAX 7000 family at this density - if your design requires faster decode paths, consider the EPM7096LC84-10 or EPM7096LC84-15 speed grades (drop-in, faster).
This page synthesizes distributor pricing, drop-in same-footprint alternatives (including faster speed grades from the Site MPN list), and practical design notes for glue-logic and 5V-system migration not collected on any single distributor page.
直接替换替代料： EPM7096LC84-7 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM7096LC84-7 （相同外形与封装尺寸） ——差异在于 Package, Mounting Type, Operating Temperature, Family, User I/O Pins.
快速对比工具——选择替代料号进行并排对比：
EPM7096LC84-10
✅ 直接替换✓ 有现货
$5.1 / 个
查看数据手册 →EPM7096LC84-15
✅ 直接替换✓ 有现货
$9.85 / 个
查看数据手册 →EPM7096LC68-7
✅ 直接替换✓ 有现货
$9.95 / 个
查看数据手册 →EPM7096LC68-15
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPM7128ELC84-7
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EPM7096LC84-7 最大额定值与电气特性
| Family | MAX 7000 |
| Macrocells | 96 |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 64 |
| Speed Grade (tPD) | 7.5 ns |
| 封装 | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| 安装类型 | Surface Mount |
| 电源电压 | 5.0 V |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Architecture | Second-generation MAX |
| I/O Logic Levels | 5.0 V TTL/CMOS-compatible |
| 工作温度 | 0C to +70C (commercial, LC suffix) |
| RoHS 状态 | Non-compliant (original Altera product, leaded PLCC package) |
| 生命周期状态 | Obsolete - PCN/PDN issued by Intel |
EPM7096LC84-7 引脚配置
| 引脚 1 | I/O — User I/O pin (macrocell input/output) |
| 引脚 2 | I/O — User I/O pin (macrocell input/output) |
| 引脚 3 | I/O — User I/O pin (macrocell input/output) |
| 引脚 4 | I/O — User I/O pin (macrocell input/output) |
| 引脚 5 | I/O — User I/O pin (macrocell input/output) |
| 引脚 6 | I/O — User I/O pin (macrocell input/output) |
| 引脚 7 | I/O — User I/O pin (macrocell input/output) |
| 引脚 8 | I/O — User I/O pin (macrocell input/output) |
| 引脚 9 | I/O — User I/O pin (macrocell input/output) |
| 引脚 10 | I/O — User I/O pin (macrocell input/output) |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — User I/O pin (macrocell input/output) |
| 引脚 13 | I/O — User I/O pin (macrocell input/output) |
| 引脚 14 | I/O — User I/O pin (macrocell input/output) |
| 引脚 15 | I/O — User I/O pin (macrocell input/output) |
| 引脚 16 | I/O — User I/O pin (macrocell input/output) |
| 引脚 17 | I/O — User I/O pin (macrocell input/output) |
| 引脚 18 | I/O — User I/O pin (macrocell input/output) |
| 引脚 19 | I/O — User I/O pin (macrocell input/output) |
| 引脚 20 | I/O — User I/O pin (macrocell input/output) |
| 引脚 21 | I/O — User I/O pin (macrocell input/output) |
| 引脚 22 | VCC — 5.0 V supply voltage |
| 引脚 23 | I/O — User I/O pin (macrocell input/output) |
| 引脚 24 | I/O — User I/O pin (macrocell input/output) |
| 引脚 25 | I/O — User I/O pin (macrocell input/output) |
| 引脚 26 | I/O — User I/O pin (macrocell input/output) |
| 引脚 27 | I/O — User I/O pin (macrocell input/output) |
| 引脚 28 | I/O — User I/O pin (macrocell input/output) |
| 引脚 29 | I/O — User I/O pin (macrocell input/output) |
| 引脚 30 | I/O — User I/O pin (macrocell input/output) |
| 引脚 31 | GND — Ground |
| 引脚 32 | I/O — User I/O pin (macrocell input/output) |
| 引脚 33 | I/O — User I/O pin (macrocell input/output) |
| 引脚 34 | I/O — User I/O pin (macrocell input/output) |
| 引脚 35 | I/O — User I/O pin (macrocell input/output) |
| 引脚 36 | I/O — User I/O pin (macrocell input/output) |
| 引脚 37 | I/O — User I/O pin (macrocell input/output) |
| 引脚 38 | I/O — User I/O pin (macrocell input/output) |
| 引脚 39 | I/O — User I/O pin (macrocell input/output) |
| 引脚 40 | I/O — User I/O pin (macrocell input/output) |
| 引脚 41 | I/O — User I/O pin (macrocell input/output) |
| 引脚 42 | VCC — 5.0 V supply voltage |
| 引脚 43 | I/O — User I/O pin (macrocell input/output) |
| 引脚 44 | I/O — User I/O pin (macrocell input/output) |
| 引脚 45 | I/O — User I/O pin (macrocell input/output) |
| 引脚 46 | I/O — User I/O pin (macrocell input/output) |
| 引脚 47 | I/O — User I/O pin (macrocell input/output) |
| 引脚 48 | I/O — User I/O pin (macrocell input/output) |
| 引脚 49 | I/O — User I/O pin (macrocell input/output) |
| 引脚 50 | I/O — User I/O pin (macrocell input/output) |
| 引脚 51 | I/O — User I/O pin (macrocell input/output) |
| 引脚 52 | GND — Ground |
| 引脚 53 | I/O — User I/O pin (macrocell input/output) |
| 引脚 54 | I/O — User I/O pin (macrocell input/output) |
| 引脚 55 | I/O — User I/O pin (macrocell input/output) |
| 引脚 56 | I/O — User I/O pin (macrocell input/output) |
| 引脚 57 | TDI — JTAG Test Data In |
| 引脚 58 | TMS — JTAG Test Mode Select |
| 引脚 59 | TCK — JTAG Test Clock |
| 引脚 60 | TDO — JTAG Test Data Out |
| 引脚 61 | I/O — User I/O pin (macrocell input/output) |
| 引脚 62 | I/O — User I/O pin (macrocell input/output) |
| 引脚 63 | I/O — User I/O pin (macrocell input/output) |
| 引脚 64 | I/O — User I/O pin (macrocell input/output) |
| 引脚 65 | I/O — User I/O pin (macrocell input/output) |
| 引脚 66 | I/O — User I/O pin (macrocell input/output) |
| 引脚 67 | I/O — User I/O pin (macrocell input/output) |
| 引脚 68 | I/O — User I/O pin (macrocell input/output) |
| 引脚 69 | I/O — User I/O pin (macrocell input/output) |
| 引脚 70 | I/O — User I/O pin (macrocell input/output) |
| 引脚 71 | GND — Ground |
| 引脚 72 | I/O — User I/O pin (macrocell input/output) |
| 引脚 73 | I/O — User I/O pin (macrocell input/output) |
| 引脚 74 | I/O — User I/O pin (macrocell input/output) |
| 引脚 75 | I/O — User I/O pin (macrocell input/output) |
| 引脚 76 | I/O — User I/O pin (macrocell input/output) |
| 引脚 77 | I/O — User I/O pin (macrocell input/output) |
| 引脚 78 | I/O — User I/O pin (macrocell input/output) |
| 引脚 79 | I/O — User I/O pin (macrocell input/output) |
| 引脚 80 | I/O — User I/O pin (macrocell input/output) |
| 引脚 81 | I/O — User I/O pin (macrocell input/output) |
| 引脚 82 | VCC — 5.0 V supply voltage |
| 引脚 83 | I/O — User I/O pin (macrocell input/output) |
| 引脚 84 | I/O — User I/O pin (macrocell input/output) |
典型应用
EPM7096LC84-7 适用于 6 应用s: Legacy 5V Bus Address Decoding, Industrial 5V Glue Logic Consolidation, Peripheral Interface Bridging, Asynchronous State Machine Controllers, VME/PCI Board Replacement Logic, Board-Level Reset and Power Sequencer.
Legacy 5V Bus Address Decoding
The EPM7096LC84-7's 96 macrocells and 7.5 ns tPD make it ideal for legacy 5V ISA/PCI bus address decoder and chip-select generation. The MAX 7000 architecture provides deterministic timing via the PIA interconnect, so address-to-CS propagation delay is guaranteed within 7.5 ns regardless of routing - critical when feeding fast peripherals or memory mapped peripherals on an 8 MHz or 16 MHz bus. Placed between the address bus and peripheral CS pins; the JTAG interface allows in-system reprogramming when the board layout is locked. Compared to a discrete 74LS/74F TTL decoder, the CPLD replaces 4-8 decoder/AND/OR packages with one IC, freeing board area for legacy 5V backplanes.
推荐
Industrial 5V Glue Logic Consolidation
The EPM7096LC84-7 consolidates dozens of 74-series glue-logic gates into one CPLD on legacy industrial PLC and process-control boards. With 96 macrocells and 64 user I/Os, it can replace 5-15 discrete SSI/MSI packages (74LS00, 74LS138, 74LS244, 74LS374) while the 5V-tolerant I/Os match existing 5V backplanes directly. The EEPROM non-volatile configuration provides instant-on behavior at power-up - critical for industrial safety and deterministic boot, unlike FPGAs that require configuration ROM boot time. The 7.5 ns tPD accommodates timing budgets up to 133 MHz for high-speed encoder counters.
推荐
Peripheral Interface Bridging
The EPM7096LC84-7 bridges incompatible peripheral interfaces (e.g., 8-bit microcontroller port to 16-bit ISA bus, or parallel port to serial UART expansion). The 64 user I/Os and 96 macrocells are sufficient to implement protocol converters, FIFOs, and handshaking logic in a single chip, while the 5V tolerance allows direct connection to legacy 5V peripheral ICs without level shifters. The JTAG ISP enables field reprogramming for protocol upgrades. The 7.5 ns tPD keeps handshaking latency below 1 bus cycle at 33 MHz, making the part suitable for real-time peripheral emulation in industrial and telecom systems.
推荐
Asynchronous State Machine Controllers
The EPM7096LC84-7 implements asynchronous state machines for reset sequencing, power-good generation, and watchdog logic in embedded systems. Each of the 96 macrocells includes a programmable flip-flop with individual clear, preset, clock, and clock-enable controls - exactly the primitives needed for Mealy/Moore state machines. The MAX 7000 PIA routing is non-blocking for asynchronous paths, so state transitions remain glitch-free under all input combinations. The 7.5 ns tPD enables sub-microsecond reset propagation chains for multi-rail processor sequencing. The 5V tolerance and PLCC-84 footprint also suit legacy telecom shelf controllers.
推荐
VME/PCI Board Replacement Logic
The EPM7096LC84-7 is widely used on legacy VMEbus and PCI add-in cards for bus arbitration, interrupt steering, and IDSEL decoding. The 5V-tolerant I/Os are essential for direct connection to VMEbus drivers and receivers (DS0026, 74LS245), eliminating level-shift logic. With 7.5 ns tPD, the CPLD meets VME DTB arbitration timing on 16-bit and 32-bit transfers without wait states. The 64 user I/Os also accommodate full VME interrupt acknowledge (IACK) Daisy-Chain driver implementations. The 84-pin PLCC footprint has been an industry-standard package for VME/PCI board designers for two decades.
推荐
Board-Level Reset and Power Sequencer
The EPM7096LC84-7 functions as a board-level reset and power-sequencing controller in multi-rail systems, generating sequenced reset pulses to FPGAs, ASICs, and microcontrollers with precise timing. With 96 macrocells, the part can implement up to 8 sequenced rails with independent delay programming, brownout detection, and watchdog timer logic. The 5V I/O tolerance allows direct connection to supervisor ICs and power-good signals from DC-DC converters. The 7.5 ns tPD provides fast response to brownout events, while the JTAG ISP allows last-minute delay adjustment without board rework. The PLCC-84 package is favored for through-hole rework on legacy boards.
推荐
推荐产品汇总
工程参考数据： EPM7096LC84-7 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC68-7 | EPM7096LC68-15 | EPM7128ELC84-7 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | PLCC-84 | PLCC-84 - same | PLCC-84 - same | PLCC-68 - smaller footprint | PLCC-68 - smaller footprint | PLCC-84 - same |
| Macrocells | 96 | 96 | 96 | 96 | 96 | 128 (+33%) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns | 15 ns | 7.5 ns | 15 ns | 7.5 ns |
| User I/O Pins | 64 | 64 | 64 | 52 (fewer due to 68-pin PLCC) | 52 (fewer due to 68-pin PLCC) | 68 |
| Logic Array Blocks (LABs) | 4 | 4 | 4 | 4 | 4 | 8 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Lifecycle Status | Obsolete (PCN/PDN issued) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Fastest speed grade in the 96-macrocell MAX 7000 84-pin PLCC family （对比 EPM7096LC84-10)
- More user I/Os than the 68-pin PLCC variants （对比 EPM7096LC68-7)
- Lower macrocell density but same MAX 7000 architecture as the 128-macrocell upgrade （对比 EPM7128ELC84-7)
设计说明
The EPM7096LC84-7 requires a stable 5.0 V supply with decoupling placed within 5 mm of each VCC pin (pins 22, 42, 82) and each GND pin (11, 31, 52, 71). Use a 100 nF ceramic + 10 uF tantalum bulk capacitor combination per rail, plus 1 uF near the JTAG TCK pin to suppress switching noise. The LC family draws ICC in the low milliamp range during static operation but can spike to ~200 mA during JTAG programming - ensure the regulator has adequate transient response. Brownout below 4.5 V may cause configuration corruption; add a TL7705 supervisor IC to drive a global reset.
For the 84-pin PLCC package, use a PLCC-84 socket (e.g., 3M 8484-21B1 or Aries 84-PRS) when designing for field programming flexibility. The PLCC-84 footprint requires rectangular SMT pads approximately 1.27 mm wide on 1.27 mm pitch, with a center pad for socket alignment. Add a JTAG header (2x5 or 2x7 0.1" pitch) connected to TCK/TMS/TDI/TDO plus GND and VCC for in-system programming via Altera ByteBlaster or USB-Blaster. Keep JTAG trace lengths under 100 mm to avoid signal integrity issues at high TCK frequencies.
Do not confuse the EPM7096LC84-7 (LC commercial temp) with the EPM7096QE84 (industrial QPFG temp) - they have different operating temperature ranges. Do not apply 3.3 V to VCC - the LC family is 5.0 V only. Do not enable global clock/clear/preset pins as user I/O without first checking the Quartus MAX 7000 device pinout file; doing so may cause configuration errors. When migrating from EPM7064 (64 macrocells) to EPM7096 (96 macrocells), recompile the design - the LAB structure differs and pin assignments may need re-mapping. Always issue a full erase before reprogramming an EEPROM-based MAX 7000 device via JTAG to prevent cell overstress.
On legacy 5V buses with fast edges (>1 ns rise time), series-terminate the I/O outputs with 33 ohm resistors to dampen reflections on long traces. The MAX 7000 output drive strength is rated at 25 mA per pin, but simultaneous switching of 8+ outputs can cause ground bounce - distribute heavily-loaded outputs across all four LABs to avoid localized GND noise. For inputs driven by 5V TTL devices, no clamping is required because the MAX 7000 LC family is 5V-tolerant; however, do not apply voltages above VCC + 0.5 V or below GND - 0.5 V. Use the dedicated JTAG pins only for JTAG operations; assigning them as user I/O requires disabling JTAG permanently and is not recommended for production.
合规信息
Original Altera MAX 7000 family PLCC-84 package uses lead (Pb) in solder balls/terminations and is therefore not RoHS compliant per Intel's product environmental compliance data. REACH compliant per EU regulation. Not AEC-Q100 qualified (commercial temp only, LC suffix). Halogen-free per JEDEC JS709. Conflict-minerals compliant per Section 1502 of the Dodd-Frank Act. For RoHS-compliant equivalent, consider MAX V CPLDs in lead-free packages.