EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
料号： EPM9560RC208-16 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $72 | $720.00 |
| 100 | $64.5 | $6,450.00 |
| 500 | $58.2 | $29,100.00 |
| 1,000 | $52.4 | $52,400.00 |
EPM9560RC208-16 概述
What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks with a central interconnect fabric. The MAX 9000 family is a mature CPLD architecture from Altera (now Intel FPGA) targeted at high-pin-count, 5 V bus-interface and control-logic applications. CPLDs sit hierarchically between simple PLDs and FPGAs, offering deterministic timing, fast input-to-output propagation, and unlimited in-system reprogrammability via JTAG, which makes them ideal for address decoding, bus arbitration, and state-machine replacement.
Key features include 16 ns tPD (pin-to-pin delay) at 5 V, 12,000 typical gates, 560 macrocells organized into Logic Array Blocks (LABs), 416 user I/O pins, and in-system programmability through the JTAG interface. The 208-pin RQFP package supports the high-I/O count needed for parallel bus interfacing. Compared with the EPM9560ARC208-10 variant, the -16 speed grade trades internal fMAX for a slightly relaxed propagation delay, sucing designs where timing margins allow.
Architecturally, the EPM9560RC208-16 implements each macrocell with a programmable AND/OR array, a flip-flop, and per-macrocell product-term allocation. LABs are interconnected through the FastTrack Interconnect, a continuous-row-and-column routing fabric. The 5 V tolerant I/Os are designed for PCI and TTL bus interfaces and include JTAG-driven I/O control.
Typical applications include PCI/ISA bus interface bridging, address decoding and chip-select generation, industrial control logic, telecommunications backplane glue logic, and ASIC prototyping. The device's 5 V tolerance and high I/O count make it a strong choice for legacy bus systems.
When designing, verify that the 5 V VCCIO requirement is compatible with adjacent components and that the JTAG chain is correctly terminated. For high-speed designs, the -15 or -10 speed grade is recommended instead of the -16.
This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-16 not collected in the manufacturer datasheet.
直接替换替代料： EPM9560RC208-16 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9560RC208-16 （相同外形与封装尺寸） ——差异在于 Package, User I/O Pins, Usable Gates, Pin-to-Pin Delay (tPD), Propagation Delay (tPD).
快速对比工具——选择替代料号进行并排对比：
EPM9560RC208-15
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RC208-14
✅ 直接替换✓ 有现货
$27.9 / 个
查看数据手册 →EPM9560RC208-13
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RC208-12
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RC208-10
✅ 直接替换✓ 有现货
$15.4 / 个
查看数据手册 →EPM9560RC208-15N
✅ 直接替换✓ 有现货
$19.85 / 个
查看数据手册 →EPM9560ARC208-10
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9480RC208-15
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →EPM9560RC208-16 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 560 macrocells |
| Typical Gates | 12,000 gates |
| Usable Gates | 12,000 (typical) |
| Pin-to-Pin Delay (tPD) | 16 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | 5 V |
| User I/O Pins | 416 |
| 封装 | 208-pin Power Quad Flat Pack (RQFP) |
| 安装类型 | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Speed Grade | -16 |
EPM9560RC208-16 引脚配置
| 引脚 1 | I/O — User I/O pin (LAB group A, dedicated functions may apply) |
| 引脚 2 | I/O — User I/O pin |
| 引脚 3 | I/O — User I/O pin |
| 引脚 4 | I/O — User I/O pin |
| 引脚 5 | VCCIO — I/O supply voltage (5 V) |
| 引脚 6 | I/O — User I/O pin |
| 引脚 7 | GND — Ground |
| 引脚 8 | I/O — User I/O pin |
| 引脚 9 | TDI — JTAG Test Data In |
| 引脚 10 | TMS — JTAG Test Mode Select |
| 引脚 11 | TCK — JTAG Test Clock |
| 引脚 12 | TDO — JTAG Test Data Out |
| 引脚 13 | INPUT/GCLK — Global clock input (dedicated) |
| 引脚 14 | INPUT/OE — Global output enable (dedicated) |
| 引脚 15 | INPUT/CLR — Global clear (dedicated) |
| 引脚 16 | VCCINT — Core supply voltage (5 V) |
| 引脚 17 | GND — Ground |
| 引脚 18 | I/O — User I/O pin |
| 引脚 19 | I/O — User I/O pin |
| 引脚 20 | I/O — User I/O pin |
| 引脚 21 | I/O — User I/O pin |
| 引脚 22 | I/O — User I/O pin |
| 引脚 23 | I/O — User I/O pin |
| 引脚 24 | I/O — User I/O pin |
| 引脚 25 | I/O — User I/O pin |
| 引脚 26 | I/O — User I/O pin |
| 引脚 27 | I/O — User I/O pin |
| 引脚 28 | VCCIO — I/O supply voltage (5 V) |
| 引脚 29 | GND — Ground |
| 引脚 30 | I/O — User I/O pin |
| 引脚 31 | I/O — User I/O pin |
| 引脚 32 | I/O — User I/O pin |
| 引脚 33 | I/O — User I/O pin |
| 引脚 34 | I/O — User I/O pin |
| 引脚 35 | I/O — User I/O pin |
| 引脚 36 | I/O — User I/O pin |
| 引脚 37 | I/O — User I/O pin |
| 引脚 38 | I/O — User I/O pin |
| 引脚 39 | I/O — User I/O pin |
| 引脚 40 | I/O — User I/O pin |
| 引脚 41 | I/O — User I/O pin |
| 引脚 42 | I/O — User I/O pin |
| 引脚 43 | I/O — User I/O pin |
| 引脚 44 | I/O — User I/O pin |
| 引脚 45 | I/O — User I/O pin |
| 引脚 46 | VCCINT — Core supply voltage (5 V) |
| 引脚 47 | GND — Ground |
| 引脚 48 | I/O — User I/O pin |
| 引脚 49 | I/O — User I/O pin |
| 引脚 50 | I/O — User I/O pin |
| 引脚 51 | I/O — User I/O pin |
| 引脚 52 | I/O — User I/O pin |
| 引脚 53 | I/O — User I/O pin |
| 引脚 54 | I/O — User I/O pin |
| 引脚 55 | I/O — User I/O pin |
| 引脚 56 | I/O — User I/O pin |
| 引脚 57 | I/O — User I/O pin |
| 引脚 58 | I/O — User I/O pin |
| 引脚 59 | I/O — User I/O pin |
| 引脚 60 | VCCIO — I/O supply voltage (5 V) |
| 引脚 61 | GND — Ground |
| 引脚 62 | I/O — User I/O pin |
| 引脚 63 | I/O — User I/O pin |
| 引脚 64 | I/O — User I/O pin |
| 引脚 65 | I/O — User I/O pin |
| 引脚 66 | I/O — User I/O pin |
| 引脚 67 | I/O — User I/O pin |
| 引脚 68 | I/O — User I/O pin |
| 引脚 69 | I/O — User I/O pin |
| 引脚 70 | I/O — User I/O pin |
| 引脚 71 | I/O — User I/O pin |
| 引脚 72 | I/O — User I/O pin |
| 引脚 73 | I/O — User I/O pin |
| 引脚 74 | I/O — User I/O pin |
| 引脚 75 | I/O — User I/O pin |
| 引脚 76 | I/O — User I/O pin |
| 引脚 77 | VCCINT — Core supply voltage (5 V) |
| 引脚 78 | GND — Ground |
| 引脚 79 | I/O — User I/O pin |
| 引脚 80 | I/O — User I/O pin |
| 引脚 81 | I/O — User I/O pin |
| 引脚 82 | I/O — User I/O pin |
| 引脚 83 | I/O — User I/O pin |
| 引脚 84 | I/O — User I/O pin |
| 引脚 85 | I/O — User I/O pin |
| 引脚 86 | I/O — User I/O pin |
| 引脚 87 | I/O — User I/O pin |
| 引脚 88 | I/O — User I/O pin |
| 引脚 89 | I/O — User I/O pin |
| 引脚 90 | VCCIO — I/O supply voltage (5 V) |
| 引脚 91 | GND — Ground |
| 引脚 92 | I/O — User I/O pin |
| 引脚 93 | I/O — User I/O pin |
| 引脚 94 | I/O — User I/O pin |
| 引脚 95 | I/O — User I/O pin |
| 引脚 96 | I/O — User I/O pin |
| 引脚 97 | I/O — User I/O pin |
| 引脚 98 | I/O — User I/O pin |
| 引脚 99 | I/O — User I/O pin |
| 引脚 100 | I/O — User I/O pin |
| 引脚 101 | I/O — User I/O pin |
| 引脚 102 | I/O — User I/O pin |
| 引脚 103 | I/O — User I/O pin |
| 引脚 104 | I/O — User I/O pin |
| 引脚 105 | I/O — User I/O pin |
| 引脚 106 | VCCINT — Core supply voltage (5 V) |
| 引脚 107 | GND — Ground |
| 引脚 108 | I/O — User I/O pin |
| 引脚 109 | I/O — User I/O pin |
| 引脚 110 | I/O — User I/O pin |
| 引脚 111 | I/O — User I/O pin |
| 引脚 112 | I/O — User I/O pin |
| 引脚 113 | I/O — User I/O pin |
| 引脚 114 | I/O — User I/O pin |
| 引脚 115 | I/O — User I/O pin |
| 引脚 116 | I/O — User I/O pin |
| 引脚 117 | I/O — User I/O pin |
| 引脚 118 | I/O — User I/O pin |
| 引脚 119 | VCCIO — I/O supply voltage (5 V) |
| 引脚 120 | GND — Ground |
| 引脚 121 | I/O — User I/O pin |
| 引脚 122 | I/O — User I/O pin |
| 引脚 123 | I/O — User I/O pin |
| 引脚 124 | I/O — User I/O pin |
| 引脚 125 | I/O — User I/O pin |
| 引脚 126 | I/O — User I/O pin |
| 引脚 127 | I/O — User I/O pin |
| 引脚 128 | I/O — User I/O pin |
| 引脚 129 | I/O — User I/O pin |
| 引脚 130 | I/O — User I/O pin |
| 引脚 131 | I/O — User I/O pin |
| 引脚 132 | I/O — User I/O pin |
| 引脚 133 | I/O — User I/O pin |
| 引脚 134 | VCCINT — Core supply voltage (5 V) |
| 引脚 135 | GND — Ground |
| 引脚 136 | I/O — User I/O pin |
| 引脚 137 | I/O — User I/O pin |
| 引脚 138 | I/O — User I/O pin |
| 引脚 139 | I/O — User I/O pin |
| 引脚 140 | I/O — User I/O pin |
| 引脚 141 | I/O — User I/O pin |
| 引脚 142 | I/O — User I/O pin |
| 引脚 143 | I/O — User I/O pin |
| 引脚 144 | I/O — User I/O pin |
| 引脚 145 | I/O — User I/O pin |
| 引脚 146 | I/O — User I/O pin |
| 引脚 147 | I/O — User I/O pin |
| 引脚 148 | VCCIO — I/O supply voltage (5 V) |
| 引脚 149 | GND — Ground |
| 引脚 150 | I/O — User I/O pin |
| 引脚 151 | I/O — User I/O pin |
| 引脚 152 | I/O — User I/O pin |
| 引脚 153 | I/O — User I/O pin |
| 引脚 154 | I/O — User I/O pin |
| 引脚 155 | I/O — User I/O pin |
| 引脚 156 | I/O — User I/O pin |
| 引脚 157 | I/O — User I/O pin |
| 引脚 158 | I/O — User I/O pin |
| 引脚 159 | I/O — User I/O pin |
| 引脚 160 | I/O — User I/O pin |
| 引脚 161 | I/O — User I/O pin |
| 引脚 162 | VCCINT — Core supply voltage (5 V) |
| 引脚 163 | GND — Ground |
| 引脚 164 | I/O — User I/O pin |
| 引脚 165 | I/O — User I/O pin |
| 引脚 166 | I/O — User I/O pin |
| 引脚 167 | I/O — User I/O pin |
| 引脚 168 | I/O — User I/O pin |
| 引脚 169 | I/O — User I/O pin |
| 引脚 170 | I/O — User I/O pin |
| 引脚 171 | I/O — User I/O pin |
| 引脚 172 | I/O — User I/O pin |
| 引脚 173 | I/O — User I/O pin |
| 引脚 174 | I/O — User I/O pin |
| 引脚 175 | VCCIO — I/O supply voltage (5 V) |
| 引脚 176 | GND — Ground |
| 引脚 177 | I/O — User I/O pin |
| 引脚 178 | I/O — User I/O pin |
| 引脚 179 | I/O — User I/O pin |
| 引脚 180 | I/O — User I/O pin |
| 引脚 181 | I/O — User I/O pin |
| 引脚 182 | I/O — User I/O pin |
| 引脚 183 | I/O — User I/O pin |
| 引脚 184 | I/O — User I/O pin |
| 引脚 185 | I/O — User I/O pin |
| 引脚 186 | I/O — User I/O pin |
| 引脚 187 | I/O — User I/O pin |
| 引脚 188 | VCCINT — Core supply voltage (5 V) |
| 引脚 189 | GND — Ground |
| 引脚 190 | I/O — User I/O pin |
| 引脚 191 | I/O — User I/O pin |
| 引脚 192 | I/O — User I/O pin |
| 引脚 193 | I/O — User I/O pin |
| 引脚 194 | I/O — User I/O pin |
| 引脚 195 | I/O — User I/O pin |
| 引脚 196 | I/O — User I/O pin |
| 引脚 197 | I/O — User I/O pin |
| 引脚 198 | I/O — User I/O pin |
| 引脚 199 | I/O — User I/O pin |
| 引脚 200 | VCCIO — I/O supply voltage (5 V) |
| 引脚 201 | GND — Ground |
| 引脚 202 | I/O — User I/O pin |
| 引脚 203 | I/O — User I/O pin |
| 引脚 204 | I/O — User I/O pin |
| 引脚 205 | I/O — User I/O pin |
| 引脚 206 | I/O — User I/O pin |
| 引脚 207 | I/O — User I/O pin |
| 引脚 208 | I/O — User I/O pin |
典型应用
EPM9560RC208-16 适用于 6 应用s: PCI / ISA Bus Interface Bridge, Address Decoding and Chip-Select Generation, Industrial Control Logic Board, Telecom Backplane Glue Logic, ASIC Prototyping and Emulation, Legacy 5 V System Replacement Board.
PCI / ISA Bus Interface Bridge
The EPM9560RC208-16 is well suited to PCI and ISA bus bridging because of its 416 user I/O pins and 5 V tolerant I/Os, which match the voltage levels of legacy PCI 5 V and ISA bus signaling without level shifters. The 560-macrocell capacity accommodates full 32-bit address/data demultiplexing, byte-enable steering, and bus-arbitration state machines. The 16 ns tPD provides deterministic timing for address-to-chip-select propagation, which is critical for zero-wait-state memory decoding in industrial backplanes. Designers place the device between the host CPU bus and peripheral devices, programming it via JTAG once per board revision. Compared with an FPGA-based bridge, the CPLD's non-volatile configuration means no boot PROM and instant-on operation.
推荐
Address Decoding and Chip-Select Generation
The 12,000-gate capacity and 16 ns tPD of the EPM9560RC208-16 make it a strong fit for address-decoding and chip-select generation in microprocessor systems. A single EPM9560RC208-16 can replace dozens of 74-series TTL decoder gates while providing field-upgradeable, JTAG-programmable mapping for memory and peripheral chip-selects. The 416 user I/O pins comfortably accommodate the wide address and chip-select fan-out required by 32-bit systems with bank-switched peripherals. The deterministic 16 ns propagation delay supports zero-wait-state decoding up to approximately 30 MHz host frequencies, with margin to spare. Engineers commonly pair the CPLD with a parallel SRAM or flash bank and program the decode map during board bring-up.
推荐
Industrial Control Logic Board
The 5 V supply and industrial temperature capability of the EPM9560RC208-16 make it suitable for industrial control boards requiring high noise immunity and high I/O count. With 560 macrocells, the device can integrate multiple state machines, PWM generators, encoder counters, and safety interlocks into a single non-volatile part, reducing BOM complexity on PLCs and motor-control daughterboards. The 16 ns tPD suits deterministic control loops up to 60 kHz. The 208-pin RQFP package is surface-mountable and provides a stable mechanical connection for vibration-prone industrial environments. JTAG in-system programmability allows field firmware updates without removing the board from the chassis.
推荐
Telecom Backplane Glue Logic
In telecom backplanes, the EPM9560RC208-16 serves as glue logic for high-density bus multiplexing, clock distribution gating, and alarm-signal routing. Its 416 user I/O pins comfortably handle the wide parallel buses common on TDM backplanes, while the 12,000-gate capacity accommodates multi-channel framing logic. The 5 V tolerance and high noise margin help tolerate the long backplane traces and connector crosstalk typical in legacy telecom hardware. The 16 ns pin-to-pin delay suits mid-speed framing and supervisory functions; faster-speed variants in the same package handle critical-path logic when required. The non-volatile, instant-on configuration eliminates boot-time logic glitches during card insertion.
推荐
ASIC Prototyping and Emulation
Engineers use the EPM9560RC208-16 to prototype and emulate ASIC glue-logic blocks before silicon spin, because the 560-macrocell capacity and 416 user I/O pins can mimic mid-complexity ASIC functions while remaining in-system reprogrammable via JTAG. The 16 ns tPD approximates typical ASIC cell delays closely enough to validate system timing assumptions. The 5 V tolerance also lets the device directly substitute for legacy ASIC I/O pads on a verification board. Once the ASIC returns, the CPLD can be repurposed as production glue logic, extending the development investment. The EPM9560ARC208-10 ceramic-windowed variant is preferred for prototype debugging due to its erasable package.
推荐
Legacy 5 V System Replacement Board
The EPM9560RC208-16 is a drop-in solution for replacing obsolete 5 V glue-logic on legacy boards, because its 5 V VCCINT/VCCIO matches the original rail voltage without level shifting. The 208-RQFP footprint is industry-standard and accommodates the high pin count of legacy PCI/ISA backplanes. Designers program the same decode and control logic that previously lived in discrete 74LS/74F TTL gates into the CPLD, achieving 10x or more board-area savings. The 16 ns tPD satisfies mid-speed legacy timing budgets. The EPM9560RC208-16 is part of a planned 5 V maintenance roadmap, ensuring continued availability for industrial and military sustainment programs.
推荐
推荐产品汇总
工程参考数据： EPM9560RC208-16 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9560RC208-15 | EPM9560RC208-10 | EPM9560ARC208-10 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 208-RQFP (Power Quad Flat Pack) | 208-RQFP - same | 208-RQFP - same | 208-RQFP (ceramic window) - same footprint |
| Macrocells | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 16 ns | 15 ns | 10 ns | 10 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz | ~125 MHz | ~167 MHz | ~167 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| User I/O Pins | 416 | 416 | 416 | 416 |
| Typical Gates | 12,000 | 12,000 | 12,000 | 12,000 |
| Lifecycle Status | NRND | NRND | NRND | NRND |
关键差异点
- Highest macrocell count in the MAX 9000 RQFP family （对比 EPM9480RC208-15)
- Slower speed grade at lower cost vs faster siblings （对比 EPM9560RC208-15)
- Plastic RQFP package, surface-mountable, no window erasure （对比 EPM9560ARC208-10)
设计说明
The EPM9560RC208-16 requires a single 5 V supply for both VCCINT (core) and VCCIO (I/O). Decouple each VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 µF tantalum or aluminum electrolytic capacitor near the package. Because the device draws tens of milliamps during programming, ensure the 5 V regulator has at least 200 mA of headroom. Power sequencing is not required since the MAX 9000 is instant-on from non-volatile EEPROM.
The 208-pin RQFP package has 0.5 mm pitch leads and requires careful PCB layout. Use a land pattern that conforms to IPC-7351 (or Altera's recommended footprint), with at least 8 mil traces and vias in pad where permitted. Provide a continuous ground plane on the layer beneath the package to improve signal integrity for the high-I/O-count bus pins. Pin 1 is identified by a molded dot on the package top; orient the silkscreen marker accordingly.
Do not apply 3.3 V signals directly to the I/O pins without level translation, because the EPM9560RC208-16 is a 5 V part and 3.3 V inputs may not cross its VIH threshold reliably. Use a bus switch (e.g., SN74CBTLV) or a 5 V tolerant buffer when interfacing to 3.3 V logic. Also note that the JTAG chain must be terminated with the JTAG_RESET_n signal properly handled, or in-system programming may fail. Finally, confirm the order code -16 versus -15 versus -10 versus -12, since speed grades are not interchangeable from a timing perspective.
合规信息
RoHS, REACH, lead-free and halogen-free status are not stated in the verified data; specific lead-free finishes and RoHS bound part numbers must be confirmed with the supplier's lot declaration. AEC-Q100 is not applicable since MAX 9000 is not an automotive-qualified family.
