EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
부품 번호: EPM9560RC208-16 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $72 | $720.00 |
| 100 | $64.5 | $6,450.00 |
| 500 | $58.2 | $29,100.00 |
| 1,000 | $52.4 | $52,400.00 |
EPM9560RC208-16 개요
What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks with a central interconnect fabric. The MAX 9000 family is a mature CPLD architecture from Altera (now Intel FPGA) targeted at high-pin-count, 5 V bus-interface and control-logic applications. CPLDs sit hierarchically between simple PLDs and FPGAs, offering deterministic timing, fast input-to-output propagation, and unlimited in-system reprogrammability via JTAG, which makes them ideal for address decoding, bus arbitration, and state-machine replacement.
Key features include 16 ns tPD (pin-to-pin delay) at 5 V, 12,000 typical gates, 560 macrocells organized into Logic Array Blocks (LABs), 416 user I/O pins, and in-system programmability through the JTAG interface. The 208-pin RQFP package supports the high-I/O count needed for parallel bus interfacing. Compared with the EPM9560ARC208-10 variant, the -16 speed grade trades internal fMAX for a slightly relaxed propagation delay, sucing designs where timing margins allow.
Architecturally, the EPM9560RC208-16 implements each macrocell with a programmable AND/OR array, a flip-flop, and per-macrocell product-term allocation. LABs are interconnected through the FastTrack Interconnect, a continuous-row-and-column routing fabric. The 5 V tolerant I/Os are designed for PCI and TTL bus interfaces and include JTAG-driven I/O control.
Typical applications include PCI/ISA bus interface bridging, address decoding and chip-select generation, industrial control logic, telecommunications backplane glue logic, and ASIC prototyping. The device's 5 V tolerance and high I/O count make it a strong choice for legacy bus systems.
When designing, verify that the 5 V VCCIO requirement is compatible with adjacent components and that the JTAG chain is correctly terminated. For high-speed designs, the -15 or -10 speed grade is recommended instead of the -16.
This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-16 not collected in the manufacturer datasheet.
드롭인 대체품: EPM9560RC208-16 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM9560RC208-16 (동일 폼 팩터 및 풋프린트) — 차이점: Package, User I/O Pins, Usable Gates, Pin-to-Pin Delay (tPD), Propagation Delay (tPD).
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM9560RC208-15
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RC208-14
✅ 드롭인✓ 재고 있음
$27.9 / 개
데이터시트 보기 →EPM9560RC208-13
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RC208-12
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RC208-10
✅ 드롭인✓ 재고 있음
$15.4 / 개
데이터시트 보기 →EPM9560RC208-15N
✅ 드롭인✓ 재고 있음
$19.85 / 개
데이터시트 보기 →EPM9560ARC208-10
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9480RC208-15
✅ 드롭인✓ 재고 있음
$24.95 / 개
데이터시트 보기 →EPM9560RC208-16 최대 정격 & 전기적 특성
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 560 macrocells |
| Typical Gates | 12,000 gates |
| Usable Gates | 12,000 (typical) |
| Pin-to-Pin Delay (tPD) | 16 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | 5 V |
| User I/O Pins | 416 |
| 패키지 | 208-pin Power Quad Flat Pack (RQFP) |
| 실장 유형 | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Speed Grade | -16 |
EPM9560RC208-16 핀 구성
| 핀 1 | I/O — User I/O pin (LAB group A, dedicated functions may apply) |
| 핀 2 | I/O — User I/O pin |
| 핀 3 | I/O — User I/O pin |
| 핀 4 | I/O — User I/O pin |
| 핀 5 | VCCIO — I/O supply voltage (5 V) |
| 핀 6 | I/O — User I/O pin |
| 핀 7 | GND — Ground |
| 핀 8 | I/O — User I/O pin |
| 핀 9 | TDI — JTAG Test Data In |
| 핀 10 | TMS — JTAG Test Mode Select |
| 핀 11 | TCK — JTAG Test Clock |
| 핀 12 | TDO — JTAG Test Data Out |
| 핀 13 | INPUT/GCLK — Global clock input (dedicated) |
| 핀 14 | INPUT/OE — Global output enable (dedicated) |
| 핀 15 | INPUT/CLR — Global clear (dedicated) |
| 핀 16 | VCCINT — Core supply voltage (5 V) |
| 핀 17 | GND — Ground |
| 핀 18 | I/O — User I/O pin |
| 핀 19 | I/O — User I/O pin |
| 핀 20 | I/O — User I/O pin |
| 핀 21 | I/O — User I/O pin |
| 핀 22 | I/O — User I/O pin |
| 핀 23 | I/O — User I/O pin |
| 핀 24 | I/O — User I/O pin |
| 핀 25 | I/O — User I/O pin |
| 핀 26 | I/O — User I/O pin |
| 핀 27 | I/O — User I/O pin |
| 핀 28 | VCCIO — I/O supply voltage (5 V) |
| 핀 29 | GND — Ground |
| 핀 30 | I/O — User I/O pin |
| 핀 31 | I/O — User I/O pin |
| 핀 32 | I/O — User I/O pin |
| 핀 33 | I/O — User I/O pin |
| 핀 34 | I/O — User I/O pin |
| 핀 35 | I/O — User I/O pin |
| 핀 36 | I/O — User I/O pin |
| 핀 37 | I/O — User I/O pin |
| 핀 38 | I/O — User I/O pin |
| 핀 39 | I/O — User I/O pin |
| 핀 40 | I/O — User I/O pin |
| 핀 41 | I/O — User I/O pin |
| 핀 42 | I/O — User I/O pin |
| 핀 43 | I/O — User I/O pin |
| 핀 44 | I/O — User I/O pin |
| 핀 45 | I/O — User I/O pin |
| 핀 46 | VCCINT — Core supply voltage (5 V) |
| 핀 47 | GND — Ground |
| 핀 48 | I/O — User I/O pin |
| 핀 49 | I/O — User I/O pin |
| 핀 50 | I/O — User I/O pin |
| 핀 51 | I/O — User I/O pin |
| 핀 52 | I/O — User I/O pin |
| 핀 53 | I/O — User I/O pin |
| 핀 54 | I/O — User I/O pin |
| 핀 55 | I/O — User I/O pin |
| 핀 56 | I/O — User I/O pin |
| 핀 57 | I/O — User I/O pin |
| 핀 58 | I/O — User I/O pin |
| 핀 59 | I/O — User I/O pin |
| 핀 60 | VCCIO — I/O supply voltage (5 V) |
| 핀 61 | GND — Ground |
| 핀 62 | I/O — User I/O pin |
| 핀 63 | I/O — User I/O pin |
| 핀 64 | I/O — User I/O pin |
| 핀 65 | I/O — User I/O pin |
| 핀 66 | I/O — User I/O pin |
| 핀 67 | I/O — User I/O pin |
| 핀 68 | I/O — User I/O pin |
| 핀 69 | I/O — User I/O pin |
| 핀 70 | I/O — User I/O pin |
| 핀 71 | I/O — User I/O pin |
| 핀 72 | I/O — User I/O pin |
| 핀 73 | I/O — User I/O pin |
| 핀 74 | I/O — User I/O pin |
| 핀 75 | I/O — User I/O pin |
| 핀 76 | I/O — User I/O pin |
| 핀 77 | VCCINT — Core supply voltage (5 V) |
| 핀 78 | GND — Ground |
| 핀 79 | I/O — User I/O pin |
| 핀 80 | I/O — User I/O pin |
| 핀 81 | I/O — User I/O pin |
| 핀 82 | I/O — User I/O pin |
| 핀 83 | I/O — User I/O pin |
| 핀 84 | I/O — User I/O pin |
| 핀 85 | I/O — User I/O pin |
| 핀 86 | I/O — User I/O pin |
| 핀 87 | I/O — User I/O pin |
| 핀 88 | I/O — User I/O pin |
| 핀 89 | I/O — User I/O pin |
| 핀 90 | VCCIO — I/O supply voltage (5 V) |
| 핀 91 | GND — Ground |
| 핀 92 | I/O — User I/O pin |
| 핀 93 | I/O — User I/O pin |
| 핀 94 | I/O — User I/O pin |
| 핀 95 | I/O — User I/O pin |
| 핀 96 | I/O — User I/O pin |
| 핀 97 | I/O — User I/O pin |
| 핀 98 | I/O — User I/O pin |
| 핀 99 | I/O — User I/O pin |
| 핀 100 | I/O — User I/O pin |
| 핀 101 | I/O — User I/O pin |
| 핀 102 | I/O — User I/O pin |
| 핀 103 | I/O — User I/O pin |
| 핀 104 | I/O — User I/O pin |
| 핀 105 | I/O — User I/O pin |
| 핀 106 | VCCINT — Core supply voltage (5 V) |
| 핀 107 | GND — Ground |
| 핀 108 | I/O — User I/O pin |
| 핀 109 | I/O — User I/O pin |
| 핀 110 | I/O — User I/O pin |
| 핀 111 | I/O — User I/O pin |
| 핀 112 | I/O — User I/O pin |
| 핀 113 | I/O — User I/O pin |
| 핀 114 | I/O — User I/O pin |
| 핀 115 | I/O — User I/O pin |
| 핀 116 | I/O — User I/O pin |
| 핀 117 | I/O — User I/O pin |
| 핀 118 | I/O — User I/O pin |
| 핀 119 | VCCIO — I/O supply voltage (5 V) |
| 핀 120 | GND — Ground |
| 핀 121 | I/O — User I/O pin |
| 핀 122 | I/O — User I/O pin |
| 핀 123 | I/O — User I/O pin |
| 핀 124 | I/O — User I/O pin |
| 핀 125 | I/O — User I/O pin |
| 핀 126 | I/O — User I/O pin |
| 핀 127 | I/O — User I/O pin |
| 핀 128 | I/O — User I/O pin |
| 핀 129 | I/O — User I/O pin |
| 핀 130 | I/O — User I/O pin |
| 핀 131 | I/O — User I/O pin |
| 핀 132 | I/O — User I/O pin |
| 핀 133 | I/O — User I/O pin |
| 핀 134 | VCCINT — Core supply voltage (5 V) |
| 핀 135 | GND — Ground |
| 핀 136 | I/O — User I/O pin |
| 핀 137 | I/O — User I/O pin |
| 핀 138 | I/O — User I/O pin |
| 핀 139 | I/O — User I/O pin |
| 핀 140 | I/O — User I/O pin |
| 핀 141 | I/O — User I/O pin |
| 핀 142 | I/O — User I/O pin |
| 핀 143 | I/O — User I/O pin |
| 핀 144 | I/O — User I/O pin |
| 핀 145 | I/O — User I/O pin |
| 핀 146 | I/O — User I/O pin |
| 핀 147 | I/O — User I/O pin |
| 핀 148 | VCCIO — I/O supply voltage (5 V) |
| 핀 149 | GND — Ground |
| 핀 150 | I/O — User I/O pin |
| 핀 151 | I/O — User I/O pin |
| 핀 152 | I/O — User I/O pin |
| 핀 153 | I/O — User I/O pin |
| 핀 154 | I/O — User I/O pin |
| 핀 155 | I/O — User I/O pin |
| 핀 156 | I/O — User I/O pin |
| 핀 157 | I/O — User I/O pin |
| 핀 158 | I/O — User I/O pin |
| 핀 159 | I/O — User I/O pin |
| 핀 160 | I/O — User I/O pin |
| 핀 161 | I/O — User I/O pin |
| 핀 162 | VCCINT — Core supply voltage (5 V) |
| 핀 163 | GND — Ground |
| 핀 164 | I/O — User I/O pin |
| 핀 165 | I/O — User I/O pin |
| 핀 166 | I/O — User I/O pin |
| 핀 167 | I/O — User I/O pin |
| 핀 168 | I/O — User I/O pin |
| 핀 169 | I/O — User I/O pin |
| 핀 170 | I/O — User I/O pin |
| 핀 171 | I/O — User I/O pin |
| 핀 172 | I/O — User I/O pin |
| 핀 173 | I/O — User I/O pin |
| 핀 174 | I/O — User I/O pin |
| 핀 175 | VCCIO — I/O supply voltage (5 V) |
| 핀 176 | GND — Ground |
| 핀 177 | I/O — User I/O pin |
| 핀 178 | I/O — User I/O pin |
| 핀 179 | I/O — User I/O pin |
| 핀 180 | I/O — User I/O pin |
| 핀 181 | I/O — User I/O pin |
| 핀 182 | I/O — User I/O pin |
| 핀 183 | I/O — User I/O pin |
| 핀 184 | I/O — User I/O pin |
| 핀 185 | I/O — User I/O pin |
| 핀 186 | I/O — User I/O pin |
| 핀 187 | I/O — User I/O pin |
| 핀 188 | VCCINT — Core supply voltage (5 V) |
| 핀 189 | GND — Ground |
| 핀 190 | I/O — User I/O pin |
| 핀 191 | I/O — User I/O pin |
| 핀 192 | I/O — User I/O pin |
| 핀 193 | I/O — User I/O pin |
| 핀 194 | I/O — User I/O pin |
| 핀 195 | I/O — User I/O pin |
| 핀 196 | I/O — User I/O pin |
| 핀 197 | I/O — User I/O pin |
| 핀 198 | I/O — User I/O pin |
| 핀 199 | I/O — User I/O pin |
| 핀 200 | VCCIO — I/O supply voltage (5 V) |
| 핀 201 | GND — Ground |
| 핀 202 | I/O — User I/O pin |
| 핀 203 | I/O — User I/O pin |
| 핀 204 | I/O — User I/O pin |
| 핀 205 | I/O — User I/O pin |
| 핀 206 | I/O — User I/O pin |
| 핀 207 | I/O — User I/O pin |
| 핀 208 | I/O — User I/O pin |
일반적인 애플리케이션
EPM9560RC208-16 적합 용도: 6 애플리케이션s: PCI / ISA Bus Interface Bridge, Address Decoding and Chip-Select Generation, Industrial Control Logic Board, Telecom Backplane Glue Logic, ASIC Prototyping and Emulation, Legacy 5 V System Replacement Board.
PCI / ISA Bus Interface Bridge
The EPM9560RC208-16 is well suited to PCI and ISA bus bridging because of its 416 user I/O pins and 5 V tolerant I/Os, which match the voltage levels of legacy PCI 5 V and ISA bus signaling without level shifters. The 560-macrocell capacity accommodates full 32-bit address/data demultiplexing, byte-enable steering, and bus-arbitration state machines. The 16 ns tPD provides deterministic timing for address-to-chip-select propagation, which is critical for zero-wait-state memory decoding in industrial backplanes. Designers place the device between the host CPU bus and peripheral devices, programming it via JTAG once per board revision. Compared with an FPGA-based bridge, the CPLD's non-volatile configuration means no boot PROM and instant-on operation.
추천
Address Decoding and Chip-Select Generation
The 12,000-gate capacity and 16 ns tPD of the EPM9560RC208-16 make it a strong fit for address-decoding and chip-select generation in microprocessor systems. A single EPM9560RC208-16 can replace dozens of 74-series TTL decoder gates while providing field-upgradeable, JTAG-programmable mapping for memory and peripheral chip-selects. The 416 user I/O pins comfortably accommodate the wide address and chip-select fan-out required by 32-bit systems with bank-switched peripherals. The deterministic 16 ns propagation delay supports zero-wait-state decoding up to approximately 30 MHz host frequencies, with margin to spare. Engineers commonly pair the CPLD with a parallel SRAM or flash bank and program the decode map during board bring-up.
추천
Industrial Control Logic Board
The 5 V supply and industrial temperature capability of the EPM9560RC208-16 make it suitable for industrial control boards requiring high noise immunity and high I/O count. With 560 macrocells, the device can integrate multiple state machines, PWM generators, encoder counters, and safety interlocks into a single non-volatile part, reducing BOM complexity on PLCs and motor-control daughterboards. The 16 ns tPD suits deterministic control loops up to 60 kHz. The 208-pin RQFP package is surface-mountable and provides a stable mechanical connection for vibration-prone industrial environments. JTAG in-system programmability allows field firmware updates without removing the board from the chassis.
추천
Telecom Backplane Glue Logic
In telecom backplanes, the EPM9560RC208-16 serves as glue logic for high-density bus multiplexing, clock distribution gating, and alarm-signal routing. Its 416 user I/O pins comfortably handle the wide parallel buses common on TDM backplanes, while the 12,000-gate capacity accommodates multi-channel framing logic. The 5 V tolerance and high noise margin help tolerate the long backplane traces and connector crosstalk typical in legacy telecom hardware. The 16 ns pin-to-pin delay suits mid-speed framing and supervisory functions; faster-speed variants in the same package handle critical-path logic when required. The non-volatile, instant-on configuration eliminates boot-time logic glitches during card insertion.
추천
ASIC Prototyping and Emulation
Engineers use the EPM9560RC208-16 to prototype and emulate ASIC glue-logic blocks before silicon spin, because the 560-macrocell capacity and 416 user I/O pins can mimic mid-complexity ASIC functions while remaining in-system reprogrammable via JTAG. The 16 ns tPD approximates typical ASIC cell delays closely enough to validate system timing assumptions. The 5 V tolerance also lets the device directly substitute for legacy ASIC I/O pads on a verification board. Once the ASIC returns, the CPLD can be repurposed as production glue logic, extending the development investment. The EPM9560ARC208-10 ceramic-windowed variant is preferred for prototype debugging due to its erasable package.
추천
Legacy 5 V System Replacement Board
The EPM9560RC208-16 is a drop-in solution for replacing obsolete 5 V glue-logic on legacy boards, because its 5 V VCCINT/VCCIO matches the original rail voltage without level shifting. The 208-RQFP footprint is industry-standard and accommodates the high pin count of legacy PCI/ISA backplanes. Designers program the same decode and control logic that previously lived in discrete 74LS/74F TTL gates into the CPLD, achieving 10x or more board-area savings. The 16 ns tPD satisfies mid-speed legacy timing budgets. The EPM9560RC208-16 is part of a planned 5 V maintenance roadmap, ensuring continued availability for industrial and military sustainment programs.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM9560RC208-16 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM9560RC208-15 | EPM9560RC208-10 | EPM9560ARC208-10 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 208-RQFP (Power Quad Flat Pack) | 208-RQFP - same | 208-RQFP - same | 208-RQFP (ceramic window) - same footprint |
| Macrocells | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 16 ns | 15 ns | 10 ns | 10 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz | ~125 MHz | ~167 MHz | ~167 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| User I/O Pins | 416 | 416 | 416 | 416 |
| Typical Gates | 12,000 | 12,000 | 12,000 | 12,000 |
| Lifecycle Status | NRND | NRND | NRND | NRND |
주요 차별점
- Highest macrocell count in the MAX 9000 RQFP family (vs EPM9480RC208-15)
- Slower speed grade at lower cost vs faster siblings (vs EPM9560RC208-15)
- Plastic RQFP package, surface-mountable, no window erasure (vs EPM9560ARC208-10)
설계 노트
The EPM9560RC208-16 requires a single 5 V supply for both VCCINT (core) and VCCIO (I/O). Decouple each VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 µF tantalum or aluminum electrolytic capacitor near the package. Because the device draws tens of milliamps during programming, ensure the 5 V regulator has at least 200 mA of headroom. Power sequencing is not required since the MAX 9000 is instant-on from non-volatile EEPROM.
The 208-pin RQFP package has 0.5 mm pitch leads and requires careful PCB layout. Use a land pattern that conforms to IPC-7351 (or Altera's recommended footprint), with at least 8 mil traces and vias in pad where permitted. Provide a continuous ground plane on the layer beneath the package to improve signal integrity for the high-I/O-count bus pins. Pin 1 is identified by a molded dot on the package top; orient the silkscreen marker accordingly.
Do not apply 3.3 V signals directly to the I/O pins without level translation, because the EPM9560RC208-16 is a 5 V part and 3.3 V inputs may not cross its VIH threshold reliably. Use a bus switch (e.g., SN74CBTLV) or a 5 V tolerant buffer when interfacing to 3.3 V logic. Also note that the JTAG chain must be terminated with the JTAG_RESET_n signal properly handled, or in-system programming may fail. Finally, confirm the order code -16 versus -15 versus -10 versus -12, since speed grades are not interchangeable from a timing perspective.
규정 준수 정보
RoHS, REACH, lead-free and halogen-free status are not stated in the verified data; specific lead-free finishes and RoHS bound part numbers must be confirmed with the supplier's lot declaration. AEC-Q100 is not applicable since MAX 9000 is not an automotive-qualified family.
