LTC2256CUJ-14 - 14-Bit 25Msps Ultralow Power 1.8V ADC | ADI
料号： LTC2256CUJ-14 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $11.49 | $11.49 |
| 10 | $10.34 | $103.40 |
| 100 | $9.2 | $920.00 |
| 500 | $8.05 | $4,025.00 |
| 1,000 | $6.9 | $6,900.00 |
LTC2256CUJ-14 概述
A pipelined ADC is a multi-stage converter that samples an analog input and distributes the conversion work across successive low-resolution flash stages; this architecture enables high sample rates with low power consumption, making pipelined ADCs the standard for communications, imaging, and instrumentation front ends. As part of the broader ADC hierarchy, pipelined converters sit between successive-approximation register (SAR) ADCs and flash ADCs in the speed/power trade-off curve, and the LTC2256 family specifically targets applications where both low power (35 mW at 25 Msps) and high dynamic range are required.
Key features of the LTC2256-14 include 800 MHz full-power input bandwidth, a flexible 1V to 2V peak-to-peak differential input range, optional internal S/H, optional data output randomizer for EMI suppression, and an optional clock duty-cycle stabilizer that relaxes clock-source requirements. The integrated SPI port allows per-channel configuration, gain/offset calibration, and output-mode selection without external hardware. Nap and full shutdown modes drop consumption to microampere levels, making this ADC well-suited for battery-powered and power-cycled systems.
Typical applications include handheld and portable test instrumentation, ultrasound front ends, low-power software-defined radio (SDR), CCD imaging, and broadband communications IF sampling. The pin-compatible LTC2257-14 (40 Msps) and LTC2258-14 (65 Msps) siblings let designers scale performance without PCB rework, and the LTC2256-12 version drops resolution to 12-bit for cost-sensitive designs.
When designing with the LTC2256CUJ-14, drive the inputs differentially with a low-jitter clock source to extract full SNR, and provide a low-noise 1.8V LDO (e.g., an ultralow-noise LDO with at least 75 dB PSRR at the ADC's Nyquist frequency) on the analog supply. Decouple AVCC with 10 µF/0.1 µF pairs close to the pins and route the digital outputs away from the analog inputs to preserve 73 dB SNR. This page synthesizes distributor pricing, drop-in alternatives, and practical layout notes not found in the manufacturer datasheet alone.
直接替换替代料： LTC2256CUJ-14 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2256CUJ-14 （相同外形与封装尺寸） ——差异在于 Package, Sample Rate, Transition Noise, RoHS Status, DNL (typical).
快速对比工具——选择替代料号进行并排对比：
LTC2257CUJ-14
✅ 直接替换✓ 有现货
$10.4 / 个
查看数据手册 →LTC2258CUJ-14
✅ 直接替换✓ 有现货
$11.4 / 个
查看数据手册 →LTC2256CUJ-12
✅ 直接替换✓ 有现货
$17.2 / 个
查看数据手册 →LTC2249IUH
✅ 直接替换✓ 有现货
$20.85 / 个
查看数据手册 →LTC2156IUP-14
✅ 直接替换✓ 有现货
$134.1 / 个
查看数据手册 →LTC2151CUJ-14
✅ 直接替换✓ 有现货
$29.1 / 个
查看数据手册 →LTC2150CUJ-14
✅ 直接替换✓ 有现货
$41.58 / 个
查看数据手册 →LTC2246HLX
✅ 直接替换✓ 有现货
$16.55 / 个
查看数据手册 →LTC2256CUJ-14 最大额定值与电气特性
| 分辨率 | 14 bit |
| Sample Rate | 25 Msps |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| 电源电压 | 1.8 V (single) |
| Power Dissipation | 35 mW at 25 Msps |
| INL | ±1 LSB (typical) |
| DNL | ±0.3 LSB (typical) |
| Transition Noise | 1.13 LSB RMS |
| SNR | 73 dB |
| Input Bandwidth (Full Power) | 800 MHz |
| Input Range | 1 Vp-p to 2 Vp-p (selectable, differential) |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS (selectable) |
| Output Supply Range (CMOS) | 1.2 V to 1.8 V |
| 封装 | 40-QFN (6 mm x 6 mm) |
| Pin/Package Code | UJ (QFN-40, 6x6 mm) |
| Configuration Interface | Serial SPI port |
| Power-Saving Modes | Nap mode, full shutdown |
| Optional Features | Clock duty-cycle stabilizer, data output randomizer |
| 工作温度 | 0C to +70C (commercial C-grade) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (PBF suffix) |
LTC2256CUJ-14 引脚配置
| 引脚 1 | AIN+ — Differential analog input (positive) |
| 引脚 2 | AIN- — Differential analog input (negative) |
| 引脚 3 | VCM — Common-mode voltage output (bypass to ground) |
| 引脚 4 | REFT — Top reference decoupling |
| 引脚 5 | REFB — Bottom reference decoupling |
| 引脚 6 | GND — Analog ground |
| 引脚 7 | AVDD — Analog 1.8V supply |
| 引脚 8 | AVDD — Analog 1.8V supply |
| 引脚 9 | CLK+ — Differential clock input (positive) |
| 引脚 10 | CLK- — Differential clock input (negative) |
| 引脚 11 | GND — Digital ground |
| 引脚 12 | OVDD — Output supply (1.2V-1.8V) |
| 引脚 13 | OVDD — Output supply (1.2V-1.8V) |
| 引脚 14 | D0 — Data output bit 0 (LSB) |
| 引脚 15 | D1 — Data output bit 1 |
| 引脚 16 | D2 — Data output bit 2 |
| 引脚 17 | D3 — Data output bit 3 |
| 引脚 18 | D4 — Data output bit 4 |
| 引脚 19 | D5 — Data output bit 5 |
| 引脚 20 | D6 — Data output bit 6 |
| 引脚 21 | D7 — Data output bit 7 |
| 引脚 22 | D8 — Data output bit 8 |
| 引脚 23 | D9 — Data output bit 9 |
| 引脚 24 | D10 — Data output bit 10 |
| 引脚 25 | D11 — Data output bit 11 |
| 引脚 26 | D12 — Data output bit 12 |
| 引脚 27 | D13 — Data output bit 13 (MSB) |
| 引脚 28 | DRY/NC — Data ready / Not connected in CMOS mode |
| 引脚 29 | CS — SPI chip select (active low) |
| 引脚 30 | SCK — SPI serial clock |
| 引脚 31 | SDI — SPI serial data input |
| 引脚 32 | SDO — SPI serial data output |
| 引脚 33 | MODE — Output mode select (CMOS / DDR CMOS / DDR LVDS) |
| 引脚 34 | SHDN — Shutdown control (active low) |
| 引脚 35 | NAP — Nap mode control (active low) |
| 引脚 36 | RAND — Output randomizer enable |
| 引脚 37 | DCS — Clock duty-cycle stabilizer enable |
| 引脚 38 | TEST — Factory test pin (leave open) |
| 引脚 39 | GND — Exposed pad analog/digital ground (EP) |
| 引脚 40 | EP — Exposed pad - must be soldered to analog ground plane |
典型应用
LTC2256CUJ-14 适用于 6 应用s: Handheld Ultrasound Imaging Receivers, Portable/Handheld Test Instrumentation, Low-Power Software-Defined Radio (SDR) IF Sampling, CCD and CMOS Image Sensor Digitizers, Broadband Communications IF Sampling, Industrial Vibration / Acoustic Monitoring.
Handheld Ultrasound Imaging Receivers
The LTC2256CUJ-14's 35 mW dissipation at 25 Msps makes it ideal for handheld ultrasound receiver arrays where multiple ADC channels must fit on a thermally constrained probe PCB. With 73 dB SNR and ±1 LSB INL, it captures the dynamic range required for diagnostic-quality imaging, while the 1.8V single-supply operation simplifies battery and USB-powered designs. The optional clock duty-cycle stabilizer and data randomizer suppress spur energy that would otherwise leak into the RF front end. Per-channel gain and offset calibration through the SPI port lets a single FPGA equalize all channels in the array at power-on.
推荐
Portable/Handheld Test Instrumentation
Battery-powered oscilloscope-style data loggers benefit from the LTC2256CUJ-14's 35 mW dissipation and 73 dB SNR to extend runtime while capturing high-fidelity waveforms up to 12.5 MHz Nyquist. The 800 MHz input bandwidth supports true undersampling of IF signals, reducing front-end analog complexity. The integrated SPI port allows the host microcontroller to switch between full-rate CMOS and DDR LVDS modes depending on display bandwidth, and the nap/shutdown modes cut idle power when the probe is disconnected. The 6x6 mm QFN footprint keeps the analog front end compact inside handheld enclosures.
推荐
Low-Power Software-Defined Radio (SDR) IF Sampling
Software-defined radios benefit from the LTC2256CUJ-14's 800 MHz full-power bandwidth, which lets designers sample wide IF strips directly without an analog mixer chain. The 73 dB SNR preserves the dynamic range needed for weak-signal demodulation, while the 1.8V single supply simplifies battery operation in field radios. The DDR LVDS output mode minimizes FPGA pin count when multiple ADCs are aggregated for MIMO front ends. SPI-configurable input range (1V to 2V p-p) supports both direct ADC and transformer-coupled IF strips.
推荐
CCD and CMOS Image Sensor Digitizers
Industrial line-scan and area-scan cameras stream pixel data through high-speed ADCs like the LTC2256CUJ-14, where 25 Msps handles VGA-class 60 fps pipelines and 73 dB SNR preserves 12-bit effective dynamic range per pixel. The 1V-to-2V programmable input range matches typical CCD output swings, removing the need for external gain stages. The 40-QFN (UJ) footprint fits compact camera head boards, and the optional data output randomizer reduces EMI that would otherwise couple back into the sensor analog path. Nap and shutdown modes drop consumption during inter-frame dead time.
推荐
Broadband Communications IF Sampling
Communications basestations and point-to-point links use the LTC2256CUJ-14 to digitize IF strips up to 12.5 MHz Nyquist with 73 dB SNR, replacing legacy analog demodulators with digital signal processing. The DDR LVDS output mode streams samples directly into modern FPGAs with reduced pin count and lower EMI. The flexible 1.2V-to-1.8V OVDD lets the same board interface 1.5V and 1.8V ASIC generations without rework. Optional clock duty-cycle stabilizer relaxes the requirement on the TCXO clock source.
推荐
Industrial Vibration / Acoustic Monitoring
Predictive-maintenance sensors in factories digitize vibration and acoustic signals with the LTC2256CUJ-14, where 35 mW enables long-life battery-powered wireless sensor nodes. The 73 dB SNR captures bearing-fault signatures clearly above the noise floor, while the 800 MHz input bandwidth handles transient impact events without aliasing. The SPI port lets the host MCU adjust input range on the fly for high-amplitude shocks. The 6x6 mm QFN footprint fits miniature sensor pods, and the shutdown mode drops current to microamps between sample windows for multi-year battery life.
推荐
推荐产品汇总
工程参考数据： LTC2256CUJ-14 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2257CUJ-14 | LTC2258CUJ-14 | LTC2256CUJ-12 | LTC2249IUH | LTC2151CUJ-14 |
|---|---|---|---|---|---|---|
| Package | QFN-40 (UJ, 6x6 mm) | QFN-40 (UJ, 6x6 mm) - same | QFN-40 (UJ, 6x6 mm) - same | QFN-40 (UJ, 6x6 mm) - same | QFN-40 (UH, 6x6 mm) - same | QFN-40 (UJ, 6x6 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Sample Rate | 25 Msps | 40 Msps (+60%) | 65 Msps (+160%) | 25 Msps (same) | 80 Msps (+220%) | 40 Msps (+60%) |
| Resolution | 14 bit | 14 bit (same) | 14 bit (same) | 12 bit (-2 bits) | 14 bit (same) | 14 bit (same) |
| Power Dissipation | 35 mW at 25 Msps | 49 mW at 40 Msps | 81 mW at 65 Msps | ~35 mW at 25 Msps | 110 mW at 80 Msps | 105 mW at 40 Msps |
| SNR | 73 dB | 73 dB | 73 dB | 70 dB | 73 dB | 73 dB |
| INL (typical) | ±1 LSB | ±1 LSB | ±1 LSB | ±0.5 LSB | ±1 LSB | ±1 LSB |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS (same) | CMOS / DDR CMOS / DDR LVDS (same) | CMOS / DDR CMOS / DDR LVDS (same) | CMOS / DDR CMOS / DDR LVDS (same) | CMOS / DDR CMOS / DDR LVDS (same) |
| SPI Port | Yes | Yes (same) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
关键差异点
- Lowest power 14-bit 25 Msps ADC in the pin-compatible LTC2258/57/56 family （对比 LTC2258CUJ-14)
- Pin-compatible 12-bit cost-down sibling （对比 LTC2256CUJ-12)
- SPI-configurable output modes vs hard-wired output on legacy ADCs （对比 LTC2150CUJ-14 (legacy))
- 800 MHz input bandwidth for direct IF sampling （对比 AD9244 (legacy))
设计说明
The 40-QFN (UJ) package has an exposed pad (EP, pin 40) that MUST be soldered to a continuous analog ground plane using multiple thermal vias for lowest ground impedance. Separate analog and digital ground planes and join them at a single point under the ADC to avoid ground-loop noise coupling into the analog inputs. Route the differential analog inputs (AIN+/AIN-) as a matched-length 100-ohm differential pair and keep them at least 3x the trace width away from any digital output bus to preserve 73 dB SNR. Place the 10 µF / 0.1 µF AVCC decoupling pair within 5 mm of the AVDD pins.
Estimated: at AVCC=1.8V and AVCC current of approximately 19.4 mA at 25 Msps, the analog supply dissipation is roughly 35 mW. Use an ultra-low-noise LDO (PSRR ≥ 70 dB at 1 MHz) such as the LT3042 to derive AVCC from a 3.3V or 5V rail; the LT3042's <1 µVrms noise will not degrade the ADC's SNR. Tie OVDD to a separate 1.2V-to-1.8V rail that matches the FPGA/ASIC I/O voltage; add a ferrite bead between OVDD and AVCC if they are derived from the same source to prevent digital switching noise coupling into analog.
Drive the differential clock inputs (CLK+/CLK-) with a low-jitter clock source (jitter < 200 fs RMS) — SNR degrades with clock jitter as SNR ≈ 20·log10(1 / (2π·fIN·tjitter)). According to the Analog Devices datasheet, the optional clock duty-cycle stabilizer (DCS) enables operation with relaxed 45/55% duty cycle clocks, which is helpful when the clock is derived from a divided FPGA PLL. Engage the data output randomizer (RAND pin) when long output traces would otherwise create EMI peaks at multiples of the sample rate.
Common pitfalls with the LTC2256CUJ-14 include: (1) using a non-low-noise LDO for AVCC, which directly adds 73 dB SNR-killing noise to the input; (2) leaving the exposed pad (EP) unsoldered, which creates thermal and grounding problems; (3) using a single-ended clock when the datasheet specifies differential; (4) forgetting the VCM bypass capacitor (typically 10 µF + 0.1 µF to ground) at pin 3 — without it the input common-mode voltage drifts and INL degrades; (5) ignoring the SPI reset sequence at power-up (CS held low during AVCC ramp) — incorrect reset locks the part in an undefined mode until power-cycled.
合规信息
The PBF/TRPBF suffix parts are RoHS compliant (lead-free). The part is a commercial-temperature-grade ADC (0C to +70C); the H-grade (LTC2256IUJ-14, -40C to +85C) and automotive variants may be available separately from Analog Devices. AEC-Q100 qualification status is not_applicable for this commercial-grade datasheet.
