FPGA & CPLD
Products (6,800+)
EPM5130WC-1AA - 128-Macrocell MAX 5000 PLD, 40ns, 50MHz | Altera
The Altera (Intel) EPM5130WC-1AA is a 128-macrocell UV-erasable programmable logic device (PLD) from the MAX 5000 family, offered in a Windowed Ceramic WQFP package with industrial-grade specifications. It features a propagation delay of 40 ns and a maximum clock frequency of 50 MHz, making it a legacy high-density general-purpose PLD for glue-logic and state-machine applications. A UV PLD (Ultra-Violet Erasable Programmable Logic Device) is a non-volatile, one-time or windowed-erasable CMOS logic device that lets designers implement custom combinatorial and registered logic. UV PLDs sit at the bottom of the programmable logic hierarchy, below EEPROM-based CPLDs and SRAM-based FPGAs, and were historically used as flexible pin-compatible replacements for 74-series TTL glue logic. The MAX 5000 family pioneered high-density, high-pin-count UV PLDs by integrating multiple PAL-like Logic Array Blocks (LABs) with a global interconnect, delivering the highest logic-to-pin ratio of any general-purpose PLD of its generation. Key features of the EPM5130WC-1AA include 128 macrocells with 48 dedicated I/O lines plus 19 dedicated inputs (68 total inputs and 48 outputs), 5 V CMOS technology, a maximum propagation delay (tPD) of 40 ns, and a maximum toggle frequency (fCNT) of 50 MHz. Programmable I/O architecture, sum-of-products logic synthesis, and JTAG-free boundary-scan testability were ahead-of-their-time features for early-1990s designs. The windowed ceramic package allows the device to be erased with UV light and reprogrammed many times, supporting iterative development. Architecturally, the EPM5130WC-1AA uses Altera's classic MAX (Multiple Array matriX) architecture: macrocells grouped into Logic Array Blocks share a programmable interconnect array (PIA), with each macrocell containing a programmable-AND/fixed-OR array, a flip-flop, and an output enable. The 5 V CMOS process ensures TTL-compatible inputs and high-drive outputs. Typical applications include legacy industrial control boards, military/aerospace systems requiring windowed-erasable PLDs, telecom interface logic, address decoding, and state-machine replacement of discrete 74LS/74F glue logic. The 50 MHz toggle rate allows it to service medium-speed bus interfaces and decoder pipelines. A key design consideration is end-of-life status: the MAX 5000 family has been NRND/obsolete for over a decade. New designs should use modern MAX II/MAX V CPLDs (e.g., EPM240, EPM570) as drop-in replacements in many cases, although pin-by-pin compatibility is rarely guaranteed. Engineers maintaining legacy systems should plan obsolescence mitigation. This page synthesizes distributor stock indicators, parametric comparison against same-family EPM5xxx variants, and practical design notes for legacy MAX 5000 systems not found in the original datasheet alone.
EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100
The Altera EPM5130WC-2 is a high-density, UV-erasable programmable logic device (PLD) from Altera's MAX 5000 family, delivering 128 macrocells with 45 ns propagation delay in a 100-terminal ceramic CQFP (R-CQFP-G100) windowed package. It is built on a CMOS technology node, supports 19 dedicated inputs and 48 bidirectional I/O lines (totaling 68 inputs and 48 outputs), and operates from a single 5V supply (4.75 V to 5.25 V) at commercial 0°C to 70°C temperature range. The windowed ceramic package allows UV erasure and reprogramming of the on-chip EEPROM configuration cells, making this part suitable for prototype development and design iteration cycles where in-circuit reprogrammability is required. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the user after manufacture, rather than being hard-wired at the fab. UV-erasable PLDs such as the MAX 5000 family sit within the broader taxonomy of programmable logic devices (PLDs -> CPLD/PLD -> programmable logic -> digital logic IC -> semiconductor). They are commonly positioned between discrete TTL/CMOS glue logic and FPGAs, offering deterministic timing, non-volatile configuration, and predictable pin-to-pin delays with far lower complexity than modern FPGAs. Key features of the EPM5130WC-2 include 128 macrocells, 45 ns worst-case pin-to-pin propagation delay (tPD), a 0.650 mm terminal pitch gull-wing CQFP-100 ceramic windowed package, single 5V supply operation, and 48 user I/O lines plus 19 dedicated inputs. The MAX 5000 architecture uses EEPROM configuration cells with multi-level AND/OR array logic, providing deterministic combinatorial and registered logic with predictable timing. The device's CMOS technology and MAX 5000 multi-level AND/OR array deliver high density for a 5V PLD with predictable, deterministic timing. Each macrocell includes a programmable register that can be configured as D, T, JK, or SR flip-flop with independent clock and reset, supporting state-machine and registered-logic designs at speeds suitable for control-plane applications. Typical applications include 5V logic replacement in legacy industrial control systems, bus-interface glue logic, address decoding for microprocessor systems, state-machine controllers, and prototype development using UV erasure. Designers favor the MAX 5000 family for its deterministic timing and rugged ceramic packaging. When designing with this device, verify the host PCB's footprint against the 100-terminal CQFP (R-CQFP-G100) land pattern with 0.650 mm pitch. Programming requires a compatible Altera programmer and a MAX+PLUS II or QUARTUS design flow; UV erasure needs a 254 nm UV lamp rated at approximately 25 W·s/cm² integrated dose. Note the part is no longer in active production - plan for last-time-buy or consider MAX 7000/MAX II family successors.
EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
The Intel (formerly Altera) EPM5130WM883B-1 is a 128-macrocell ultraviolet-erasable programmable logic device (UV PLD) from the MAX 5000 family, supplied in a ceramic-sealed CQFP-100 package and qualified to MIL-STD-883 Class B for high-reliability and military-aerospace applications. It is fabricated in CMOS technology and operates from a single 4.5V to 5.5V supply (nominal 5V), delivering a propagation delay of 55 ns and supporting clock frequencies up to 33.3 MHz. The architecture is built around 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), giving the part a regular, deterministic structure well suited to glue-logic replacement, state-machine implementation and decoder functions in legacy and ruggedised systems. A programmable logic device (PLD) is a non-volatile digital IC whose logic function and interconnect pattern are defined after manufacture by user programming. PLDs sit in the broader hierarchy: PLD -> SPLD/CPLD -> programmable logic -> digital semiconductor. The MAX 5000 series in particular is a Classic SPLD/EPLD line, predecessor to the modern MAX 7000 and MAX II/MAX V CPLD families. Erasable variants such as the EPM5130WM can be erased by exposing the die to UV light through the quartz window of the ceramic package, allowing the same part to be reprogrammed many times - valuable for prototyping and for low-volume production where mask-programmed logic is uneconomic. Key features include 128 macrocells, 19 dedicated inputs and 48 bi-directional I/O pins, one global clock input, and shared input/clock pins with programmable polarity. The I/O structure supports shared inputs and clocks to maximise usable pins and to simplify state-machine and counter designs. With a 55 ns propagation delay the device targets asynchronous logic at moderate frequencies and synchronous logic below 33.3 MHz. The 883B suffix indicates processing in accordance with MIL-STD-883, Test Method Standard for Microcircuits, and the additional '-1' speed/grade suffix denotes a specific propagation-delay bin within the 883B-screened family. The MAX 5000 architecture uses a sum-of-products AND/OR plane plus output macrocells with selectable registered/combinational modes and programmable feedback, allowing implementation of up to 128 product-term logic expressions per device. The 8 LABs feed a central PIA that routes signals between blocks, providing predictable timing that does not depend on placement - a useful property for safety-critical and DO-254 style designs. The device is non-volatile (UV-erasable rather than SRAM-based), so it powers up into the programmed configuration with no external boot memory. Typical applications include military and aerospace avionics, industrial control glue logic, telecom line-card interface logic, instrumentation front-end state machines, and legacy system redesigns where the original PAL/GAL and bipolar PLD must be replaced by a denser, CMOS-equivalent part. The MIL-STD-883B screening also makes it a candidate for ruggedised industrial platforms requiring wider temperature operation and guaranteed baseline reliability. The 'WM' package code denotes a ceramic windowed CQFP-100 suitable for field re-programmability. When designing with the EPM5130WM883B-1, plan power sequencing to avoid latch-up: VCC must ramp monotonically to 5V ±10% before any input or I/O is driven. Inputs are TTL-compatible, but unused inputs should be tied to VCC or GND through a resistor to avoid floating-rail noise. The ceramic windowed package must be shielded from ambient light after programming; opaque labels are recommended. This page synthesises distributor pricing, MIL-STD-883B qualification notes, and pin-compatible drop-in guidance not aggregated on a single manufacturer page.
EPM5130WM883B-2 - 128-Macrocell MAX 5000 UV PLD | Altera | Military
The Altera (now Intel) EPM5130WM883B-2 is a 128-macrocell high-speed, high-density UV-erasable programmable logic device (UV PLD) from the MAX 5000 family, packaged in a military-grade (883B) form factor. It is built on a CMOS process and delivers a worst-case propagation delay of 45 ns (tPD, -2 speed grade), making it suitable for glue-logic and state-machine replacement in legacy industrial and military systems. The device is organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), with 19 dedicated inputs and 48 user I/O lines for a total of 68 inputs and 48 outputs. A programmable logic device (PLD) is a digital IC whose logic function is defined by the customer after manufacture, typically via non-volatile or UV-erasable fuses/antifuses, sitting in the broader hierarchy of programmable logic -> logic IC -> integrated circuit. MAX 5000 devices are organized as an AND/OR macrocell array optimized for combinational and registered logic, with the -883B suffix indicating MIL-STD-883 Class B processing for extended environmental and reliability qualification. The -2 speed grade designates a 45 ns tPD, the fastest bin of the EPM5130 family (the non-883B EPM5130WM883B runs at 55 ns). Key features include 128 macrocells, 8 LABs, 48 I/O pins, 1 dedicated clock input, and shared inputs/clocks routed through the PIA. The UV-erasable window allows field re-programmability, useful for design iteration on legacy boards. Per the Altera datasheet family document, the EPM5130 is supported by the MAX+PLUS II development environment. Typical applications include military/aerospace digital control, legacy industrial PLC glue logic, address decoding, bus interfacing, and state-machine consolidation in avionics and ground-vehicle platforms. The 883B processing makes the device especially suited for environments requiring controlled components. When designing with this part, verify package pinout against the Altera MAX 5000 datasheet - legacy PLDs often share the same JTAG-style programming interface and require a 12V VPP programming pulse during UV-erase/reset cycles. Pin-compatible MAX 5000 variants (EPM5130WC-1, EPM5130QC-1, EPM5130LC) share logic architecture but differ in package and speed. This page synthesizes distributor pricing, military-grade cross-references, and drop-in MAX 5000 alternatives not consolidated in the original Altera datasheet.
EPM5192-1LC - MAX 5000 CPLD 192-Macrocell 62.5MHz | Altera
The Altera EPM5192-1LC is a 192-macrocell member of the classic MAX 5000 high-speed, high-density programmable logic device family, supplied in a ceramic-windowless ceramic (LC) J-leaded chip-carrier package. It integrates 3,750 usable gates, 192 macrocells and 64 user I/O pins, with a worst-case pin-to-pin propagation delay in the -1 speed grade suited to combinatorial and registered glue-logic tasks at up to 62.5 MHz internal operation. The MAX 5000 architecture combines an EPROM-based AND plane feeding a fixed OR/macrocell array, giving non-volatile, in-system-reprogrammable logic that retains its configuration without battery backup. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that integrates multiple PAL/GAL-style macrocell blocks on a single die. Within the broader taxonomy, CPLDs sit alongside simple PLDs as the "instant-on, deterministic-timing" branch of programmable logic, distinct from SRAM-loaded FPGAs that require a configuration device. MAX 5000 specifically targets high logic-to-pin density in 5 V systems, historically used as bus decoders, address mapping, peripheral glue, and state-machine controllers. Designers choose this family for deterministic propagation delays, zero boot time, and excellent pin-locked retrofits into legacy 5 V backplanes. Key features of the EPM5192-1LC include 192 macrocells across four logic-array blocks (LABs), a programmable interconnect array (PIA), 64 bi-directional I/O pins with individually programmable direction and pull-up resistors, JTAG-compliant IEEE 1149.1 boundary-scan support, and an erasable EPROM process technology that is one-time programmable after window erasure. Power consumption is approximately 0.6 mA standby (outputs disabled) and a few hundred mA dynamic depending on toggle rate and frequency, all on a single 5 V supply. Typical applications for the EPM5192-1LC include 5 V bus arbitration and address decoding in VME/PCI industrial backplanes, peripheral glue logic in legacy telecom and instrumentation chassis, ISA-bus address mapping, custom state machines for motor control, and pin-locked drop-in replacements for vintage 22V10/26V12-style designs requiring higher macrocell count. The 64-pin ceramic J-lead package preserves thermal margin for industrial-grade environments. Designers migrating from 5 V to 3.3 V logic should consider the newer MAX 7000AE or MAX II families; EPM5192-1LC is intended strictly for 5 V legacy systems and is recommended for long-life industrial, military and aerospace retrofits where parts longevity matters more than state-of-the-art density.
EPM51929C - Altera MAX 5000 High-Density EPLD | Intel
The Intel (formerly Altera) EPM51929C is a member of the MAX 5000 family of high-speed, high-density Erasable Programmable Logic Devices (EPLDs) designed for integration of multiple programmable logic functions on a single CMOS device. The MAX 5000 family introduced a multi-array matrix architecture, combining fast 20-pin PAL-style logic blocks with a programmable interconnect network, enabling designers to replace dozens of discrete SSI/MSI logic parts with one device. The part is classified as FPGA/CPLD-class programmable logic and is documented in Altera's MAX 5000 datasheet family. A programmable logic device (PLD/EPLD) is a semiconductor integrated circuit that can be configured by the end-user to implement custom digital logic functions. PLDs occupy the intermediate tier between fixed-function ASICs and discrete logic gates: they offer integration density (replacing many 74LS/74HC parts), short development cycles, and in-system reprogrammability for legacy designs. EPLDs use UV-erasable EPROM cells for non-volatile configuration, retaining their logic when power is removed. Within the broader taxonomy: PLD -> EPLD -> CMOS EPLD -> MAX 5000 family -> Altera programmable logic. The EPM51929C specifically targets glue-logic and bus-interface applications requiring high pin count and moderate logic density. Key characteristics include high-density logic integration, multiple macrocell and expander-product-term structures typical of the MAX 5000 family, and CMOS technology for low static power consumption. The MAX 5000 family was widely deployed in late-1980s and 1990s bus-interface, address-decoding, and state-machine designs. Programmability is achieved via EPROM cells, requiring UV erasure for re-programming. The part is sourced today primarily through the obsolete/legacy distribution channel, making it a target for aftermarket and franchised stocking distributors. Typical applications for the EPM51929C include address decoding and chip-select generation in 80x86 microprocessor systems, DMA and interrupt controller glue logic, peripheral bus arbitration in VME/Multibus designs, state-machine controllers in industrial automation, and legacy system refresh where the original MAX 5000 design must be maintained without PCB redesign. The part's high pin count allows integration of multiple wide decoding functions in one package. When designing with the MAX 5000 family, note that parts are programmed using industry-standard PLD programmers that support the JEDEC fuse-map format. UV erasure takes approximately 20-30 minutes under a 12,000 uW/cm^2 UV lamp at 253.7 nm. Static power consumption is low but I/O drive characteristics must be checked against the specific bus interface (TTL/CMOS) used in the target design.
EPM5192AGC - MAX 5000 EPLD, 192 Macro, 84-Pin PGA | Altera
The Altera EPM5192AGC is a high-speed, high-density CMOS EPLD from the legacy MAX 5000 family, providing 192 macrocells and programmable logic capacity in an 84-pin ceramic PGA package. Marketed as part of the MAX 5000 series "High-Speed, High-Density" line, the device delivers the classic Altera second-generation architecture with pin-compatible speed grades and pin counts spanning the entire EPM5192 family. The "AG" suffix denotes the ceramic PGA package family, while the trailing "C" indicates the commercial speed grade. A UV-erasable / OTP Complex PLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR arrays with a fixed OR array and is configured by storing charge on floating-gate transistors. The MAX 5000 family sits within the broader taxonomy of programmable logic: PLD -> EPLD/CPLD -> CMOS EPLD -> MAX series, occupying the same architectural lineage as the classic PAL/GAL devices but with higher usable density and deterministic timing. The MAX 5000 family uses a sum-of-products architecture combined with a flexible macrocell, and is electrically erasable (UV window for UV parts, OTP for windowless parts). Key features include 192 macrocells, 100% factory-tested operation across commercial and industrial temperature ranges, programmable security bit for design protection, and a programmable interconnect fabric supporting high-speed logic. The device is fabricated in CMOS technology, delivering low static power consumption compared to bipolar predecessors such as the classic 22V10 PAL family. Multiple speed grades are offered within the EPM5192 base part number. Typical applications include legacy glue logic replacement, bus interface bridging, address decoding, state-machine implementation, and pin-compatible upgrades for older PAL/PLD designs in industrial control, telecommunications infrastructure, and military/aerospace systems. The EPM5192 family is frequently used in long-lifecycle systems where design stability, established silicon, and toolchain maturity are prioritized over cutting-edge density. When designing with this device, confirm the exact speed grade, package variant (PGA window vs. windowless), and operating-temperature range required by the end system, because the family supports multiple variants such as EPM5192AGC-15 and EPM5192AGC-20 that share the same package and macrocell count but differ in propagation-delay specifications. Designers should also confirm programming hardware and software support (e.g., legacy MAX+PLUS II or Altera/Intel-compatible toolchains), as the device is part of a mature, legacy product family.
EPM5192AGC-15 - 192-Macrocell MAX 5000 EPLD | Altera | 15ns
The Altera EPM5192AGC-15 is a high-density, UV-erasable erasable programmable logic device (EPLD) from the classic MAX 5000 family, delivering 192 macrocells, 72 inputs, and a 15 ns pin-to-pin propagation delay in a ceramic PGA package. It belongs to the MAX 5000 series of high-speed, high-density CMOS EPLDs that brought register-rich programmable logic to bus-interface, glue-logic, and state-machine designs in the 1990s and early 2000s. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that uses EPROM/EEPROM storage cells to retain configuration, positioned hierarchically between a PAL/GAL (simple PLD) and a true FPGA. Within the broader taxonomy of programmable logic, EPLDs sit above simple PLDs but below FPGAs in logic density, while offering predictable timing and instant-on behavior at power-up. The MAX 5000 family is the legacy Altera product line that preceded the MAX 7000/MAX II families; devices are programmed via a JTAG-style or dedicated programming interface and are commonly supplied in windowed ceramic packages for prototype/development use. Key specifications include 192 macrocells organized in logic array blocks, 64 I/O pins plus 7 dedicated input pins for a total of 72 inputs, a 15 ns worst-case pin-to-pin propagation delay (-15 speed grade), and CMOS technology operating from a 5 V supply. The device supports in-system programmability through the Altera programming hardware, and the ceramic PGA package is windowed for UV erasure during development. Compared with its slower siblings (EPM5192AGC-20 at 20 ns and EPM5192AGC-25 at 25 ns), the -15 speed grade is the fastest variant in the family and is targeted at high-speed bus-interface applications. Typical applications include 32-bit microprocessor bus decoding, state-machine controllers, address decoding for memory subsystems, and replacement of multiple discrete TTL/CMOS glue-logic packages. The high input count (72 inputs) makes the EPM5192 well suited to monitoring multiple control signals in parallel, while the predictable 15 ns delay allows replacement of multiple 74LS/74F-series decoders with a single device. When designing with this part, ensure that the 5 V VCC supply is well decoupled and that the ceramic PGA socket accommodates the device's pin pattern. Note that the EPM5192 family is mature/legacy; new designs typically migrate to MAX 7000AE or MAX II devices, and long-term availability is constrained. This page synthesizes distributor pricing, drop-in alternative guidance, and practical design notes that complement the Altera datasheet and help engineers source or replace this legacy EPLD in maintenance and modernization projects.
EPM5192AGC-20 - MAX 5000 EPLD, 192 Macrocells | Altera (Intel)
The Intel (formerly Altera) EPM5192AGC-20 is a high-density, high-speed CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, providing 192 macrocells and 12,000 usable gates in a ceramic-windowed PGA (Pin Grid Array) ceramic package. It operates at a 20 ns pin-to-pin propagation delay, making it suitable for glue-logic, bus-interface, and high-speed state-machine replacement of multiple discrete TTL/CMOS devices. A MAX 5000-series EPLD is a member of the electrically-erasable programmable logic device (EEPLD) family. In the broader component taxonomy, an EPLD sits under programmable logic devices (PLDs) -> programmable logic -> digital logic ICs. MAX 5000 devices use a programmable AND/OR macrocell architecture with non-volatile EEPROM configuration memory, so designs retain their pattern after power-down without an external boot PROM - unlike SRAM-based FPGAs which require a configuration flash. Each macrocell contains a programmable AND plane feeding a fixed OR term, an output register, and a feedback path, allowing both combinatorial and registered logic to be implemented. Key features of the EPM5192 include 192 macrocells, 12,000 usable gates, a 20 ns tPD (pin-to-pin delay), fCNT up to 100 MHz counter frequency, and 96 dedicated I/O pins organized into 8 LABs (Logic Array Blocks). Per the Altera MAX 5000 datasheet, the device supports 5 V in-system programmability via the IEEE 1149.1 JTAG interface, allowing reconfiguration without removal from the board. An enhanced security bit prevents pattern read-back, protecting proprietary designs. Typical applications include high-speed glue logic between microprocessors and peripherals, bus arbitration and address decoding, state-machine replacement for legacy 74LS/74F TTL, and industrial control sequencers. The 20 ns tPD makes it appropriate for systems clocked up to ~33 MHz without pipeline insertion. When designing with the EPM5192AGC-20, verify that the target application does not exceed 5.5 V VCC. Use a ceramic-socketed PGA footprint to take advantage of windowed UV erasure during prototyping. The ceramic 'G' package is rated for commercial 0C to 70C operation; for industrial temperatures use the equivalent -1 or -2 speed grade in a plastic package.
EPM5192AGC84-15 - 192-Macrocell UV PLD, 15ns | Altera MAX 5000
The Altera EPM5192AGC84-15 is a 192-macrocell UV-Erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 family, housed in an 84-pin Ceramic PGA (Pin Grid Array) package. This CMOS device provides 192 logic macrocells organized into 12 Logic Array Blocks (LABs), 64 user I/O pins, and 7 dedicated inputs, supporting combinational and registered logic with a propagation delay of 15 ns (commercial grade) and a maximum internal clock frequency of 83.3 MHz. It operates from a single 4.5 V to 5.5 V supply, with the -15 speed grade denoting a 15 ns pin-to-pin delay. What is a UV-erasable/OTP PLD? A UV-Erasable Complex PLD (Programmable Logic Device) is a non-volatile, one-time-programmable logic IC whose AND/OR array fuse links can be cleared by exposing the die to ultraviolet light through a quartz window, then re-programmed in a dedicated device programmer. The OTP suffix indicates one-time programmable packaging without an erasure window, while the UV variant retains the quartz lid. The MAX 5000 sits in the historical taxonomy: PLD -> CPLD (Complex PLD) -> MAX family -> UV-erasable high-density logic, predating modern SRAM-based FPGAs. Key features include 192 macrocells with configurable D/T/JK flip-flops, 64 bidirectional I/O lines with TTL/CMOS-compatible thresholds, an internal global clock network with synchronous/asynchronous operation, and a 5 V CMOS process that delivers 15 ns propagation delay with low power consumption. The 84-pin ceramic PGA package offers robust thermal performance for industrial and military temperature grades. Architecturally, the MAX 5000 family uses a sum-of-products PLA structure with distributed AND/OR arrays feeding each macrocell, allowing up to 32 product terms per macrocell. The 12 interconnected LABs provide high integration density for glue logic, address decoding, bus arbitration, and state-machine consolidation in 5 V systems. Typical applications include 5 V bus-interface glue logic, address decoding and interrupt priority encoding in 8086/Motorola 68000 systems, state-machine and sequencer consolidation in industrial controllers, and high-reliability avionics and military systems requiring UV-reprogrammable logic. The -15 speed grade (15 ns tPD) suits most glue-logic tasks where 25 ns devices would be too slow. When designing with this part, note that the 84-pin ceramic PGA package requires a through-hole socket and is significantly larger than modern QFP/BGA CPLDs; verify PCB layout and programmer compatibility before specifying. The CMOS process requires careful ESD handling during programming and in-system integration.
EPM5192AGC84-20 - 192-Macrocell MAX 5000 UV PLD | Altera | 84-CPGA
The Altera EPM5192AGC84-20 is a CMOS UV-Erasable/OTP Complex Programmable Logic Device (PLD) from the Altera MAX 5000 family, packaged in an 84-pin Ceramic Pin Grid Array (CPGA, package code WPGA) and qualified for commercial temperature grading. It integrates 192 macrocells, 64 user I/O lines, and 7 dedicated inputs, and is rated for a maximum clock frequency of 66.7 MHz with a 20 ns pin-to-pin logic delay. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix on a single die. CPLDs sit between discrete TTL/CMOS glue logic and larger FPGAs in the programmable-logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic. They are valued for deterministic timing, zero-configuration latency, and high pin-to-pin drive strength, which makes them ideal for address decoding, bus interfacing, and state-machine replacement in legacy industrial designs. Key features of the EPM5192AGC84-20 include 192 macrocells (delivering up to ~7,500 usable gates), 64 bi-directional I/O pins organized into 4 I/O banks, 7 dedicated global input pins (GCLK, OE1, OE2, OE3, OE4, CLR, PRE), in-system UV-erase window (ceramic package), and 5-Volt CMOS I/O compatible with TTL levels. The "-20" speed grade corresponds to tPD = 20 ns and fMAX = 66.7 MHz. The device is built on Altera's classic MAX (Multiple Array matriX) architecture, which arranges macrocells into Logic Array Blocks (LABs) connected by a continuous programmable interconnect. The ceramic CPGA package is hermetic and UV-transparent, allowing erasure under a UV lamp; an OTP window is included for production programming. The design supports both combinatorial and registered logic with per-macrocell D/T/JK flip-flop configuration. Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding for microprocessor and DSP systems, peripheral replacement (decoders, multiplexers, state machines), and prototype-to-production migration where deterministic timing and instant-on behavior are required. Its 84-pin CPGA is also well suited to through-hole industrial backplanes and military-style card cages where ceramic packaging is preferred. When designing with this part, verify that the CPGA land pattern matches your socket or PCB footprint; ceramic CPGA sockets are specialty items and may have long lead times. For new designs, modern Altera/Intel MAX II or MAX V devices in PLCC/QFP packages are recommended, but the EPM5192AGC84-20 remains the canonical drop-in for legacy systems requiring UV erase. This page synthesizes distributor pricing, real-time stock, ceramic-package handling guidance, and parametric drop-in alternatives that are not collected in the manufacturer datasheet.
EPM5192AJC-15 - MAX 5000 EPLD, 192 Macrocells, PLCC-84 | Intel
The Intel (formerly Altera) EPM5192AJC-15 is a high-density, high-speed Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, delivering 192 macrocells, 100% connectivity, and a 15 ns pin-to-pin logic delay in a 84-pin PLCC (J-lead) package. The part operates from a 5 V supply and supports in-system programmability via Altera's MAX+PLUS II development environment, making it a drop-in upgrade for legacy MAX 5000 designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic component that combines AND/OR arrays with output macrocells, bridging the architectural gap between simple PLDs and complex CPLDs. The MAX 5000 family sits in the broader taxonomy of programmable logic: programmable logic -> CPLD/EPLD -> MAX family -> MAX 5000 series, and historically served glue-logic, bus-interface, and state-machine roles before being superseded by modern MAX II, MAX V, and MAX 10 devices that use LUT-based architectures and flash or SRAM configuration. Key features include 192 macrocells, 100% connectivity, 15 ns combinational propagation delay (tPD), a 5 V VCC tolerance on I/O, and an ultraviolet-erasable windowed package (the "W" variant is windowed; the J-lead ceramic PLCC "JC" is non-windowed production package). The architecture provides up to 4 product terms per macrocell with a configurable XOR gate for polarity control, allowing efficient implementation of wide AND-OR-INVERT logic functions. Densities in the family range from 32 to 192 macrocells, and the EPM5192 sits at the top of the MAX 5000 density range. The MAX 5000 architecture uses a sum-of-products PLA structure with a global interconnect that guarantees 100% routability of all logic - a hallmark Altera design differentiator versus PAL-style fusemap devices. This deterministic routing eliminates place-and-route iterations common in modern FPGA flows and allows the MAX+PLUS II fitter to deliver consistent timing closure across revisions. The trade-off is lower logic density and higher per-macrocell cost versus LUT-based FPGAs, but for legacy 5 V designs the MAX 5000 family remains a proven, long-lived platform. Typical applications include legacy 5 V bus-interface glue logic, address decoding and chip-select generation, state-machine and sequencer logic, peripheral controllers in industrial and telecom backplanes, and replacement of multiple discrete PAL/GAL devices. The 84-pin PLCC package and 5 V operation also make the EPM5192AJC-15 compatible with older through-hole and socketed designs where board rework is impractical. When designing with this device, ensure the MAX+PLUS II toolchain (or modern compatible programmer) is available and verify availability of a 5 V source. Note that Intel/Altera MAX 5000 devices have been in maintenance status for many years; verify long-term supply before new designs. The "-15" speed grade corresponds to a 15 ns tPD; the "-20" and "-25" grades are slower and may be substituted in non-timing-critical sockets. This page synthesizes distributor stock data, same-family pin-compatible alternatives, and practical migration guidance not found in the original datasheet.
EPM5192AJC-25 - MAX 5000 192-Macrocell EPLD, 25ns | Altera
The Intel / Altera EPM5192AJC-25 is a 192-macrocell, high-density, high-speed Erasable Programmable Logic Device (EPLD) from the legacy MAX 5000 family, housed in a 68-pin PLCC (AJC) windowed ceramic package with 25 ns pin-to-pin propagation delay. The MAX 5000 family was Altera's second-generation EPLD architecture, offering non-volatile UV-erasable programmability, predictable timing, and 5 V tolerant CMOS I/O targeted at glue-logic, bus-interface, and state-machine integration in through-hole industrial designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR array architecture with macrocell-based output logic, falling within the broader hierarchy of programmable logic devices (PLD) -> EPLD/CPLD -> complex programmable logic. EPLDs sit between simple PAL/GAL devices and modern SRAM-based FPGAs in terms of density and are characterized by deterministic propagation delay that does not depend on routing path length - a critical property for asynchronous bus interfaces and decoder logic. Key features include 192 macrocells organized into multiple Logic Array Blocks (LABs), 100% factory-tested operation, 5 V CMOS I/O with TTL-compatible inputs, programmable output macrocells with configurable flip-flops, and a maximum propagation delay of 25 ns (tPD). The ceramic windowed PLCC package supports UV erasure for prototype and development cycles, while the AJC suffix denotes the PLCC-68 ceramic windowed form factor with industrial-grade operating temperature range. The MAX 5000 architecture uses a classic EPROM-based AND/OR plane feeding output macrocells with selectable registered/combinational modes. Unlike SRAM-based FPGAs, the device requires no external boot PROM, powers up in a defined state, and retains configuration indefinitely. The 25 ns speed grade positions this part for legacy 25-33 MHz bus interfaces rather than modern high-speed designs. Typical applications include legacy PC/AT bus decode logic, peripheral controllers (DMA, interrupt, bus arbitration), industrial state machines, military/aerospace systems (the J-grade marking indicates MIL-STD-883 processing), and prototyping platforms for newer MAX 7000/MAX II designs. Engineers working on long-lifecycle defense and aerospace equipment frequently retain MAX 5000 designs due to form-fit-function stability. When designing with this EPLD, ensure the propagation delay budget accounts for both tPD and tCO (clock-to-output) timing - consult the datasheet for the exact derating curves at junction temperatures above 70°C. UV erasure requires a windowed ceramic package; production plastic-package equivalents (EPM5192AQI, EPM5192AQC) offer one-time programmable (OTP) replacements with identical footprint but no window. This page synthesizes distributor pricing, drop-in same-family alternatives, and design considerations not consolidated in the original Altera datasheet.
EPM5192AJC84-15 - MAX 5000 CPLD, 192 Macrocells, 84-pin PLCC | Altera
The Altera EPM5192AJC84-15 is a UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 192 macrocells in an 84-pin PLCC (J84C) windowed ceramic package. It operates from a single 5V supply with a propagation delay of 15 ns and a maximum clock frequency of 83.3 MHz, making it suitable for high-speed glue-logic and state-machine integration. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple SPLDs/GALs and large FPGAs in the programmable logic hierarchy (SPLD -> CPLD -> FPGA -> programmable logic). It typically contains multiple PAL-like logic blocks interconnected by a central programmable switch matrix, with non-volatile storage that retains configuration without external memory. The MAX 5000 family was Altera's second-generation high-density EPLD line (the second 'M' family), succeeding the classic MAX 7000 and MAX 3000 lines that became industry workhorses for bus-interface and address-decoding glue logic. Key features include 192 macrocells (each containing a programmable AND/OR array with a flip-flop), 5V CMOS technology, UV-erasable windowed package for re-programmability, and pin-to-pin compatibility across the MAX 5000 series. The 15 ns propagation delay supports synchronous designs up to the rated 83.3 MHz fMAX, and the device supports both combinatorial and registered logic through its macrocell register option. Architecturally, the EPM5192 uses a classic sum-of-products PLA structure with a global interconnect matrix that delivers consistent, deterministic timing across all 192 macrocells. The CMOS EPROM-based configuration cell stores the logic pattern, and the ceramic windowed package (designated 'JC' with quartz window for UV erasure) is intended primarily for prototype development; production units typically migrate to the plastic 'PC' one-time-programmable package. Typical applications include bus address decoding, state-machine controllers, glue logic between microprocessors and peripherals, and legacy industrial-control designs. The wide 5V tolerance also makes it useful as a level shifter between TTL and CMOS logic families on legacy backplanes. When designing with the EPM5192, ensure the 5V VCC rail is well-decoupled with 0.1 uF ceramic capacitors near each supply pin, and verify that all inputs respect the 5.5V absolute maximum rating. For new designs, consider that the MAX 5000 family is mature/EOL — confirm long-term availability before committing to volume production. This page synthesizes distributor stock data, parametric drop-in alternatives, and practical MAX 5000 design notes not collected in any single manufacturer datasheet.
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
The Altera EPM5192AJC84-20 is a 192-macrocell UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC J-Lead, WQCCJ) package with a 33 ns propagation delay and a 66.7 MHz maximum clock frequency. It operates from a single 4.75 V to 5.25 V supply, offers 7 dedicated inputs and 64 user I/O lines, and is fabricated on a CMOS UV-erasable switch-matrix process that allows in-system erasure and re-programming using an ultraviolet lamp. What is a UV-erasable CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on digital IC that implements glue logic, bus arbitration, state machines, and address decoding in a single chip. The UV-erasable (windowed) variant adds a quartz window above the die that lets an external UV lamp reset the on-chip EEPROM-like switches, so the same physical package can be re-programmed many times during prototyping. Within the broader taxonomy, a CPLD belongs to programmable logic devices (PLD), which themselves sit under digital logic ICs and semiconductor devices. Key features include 192 macrocells arranged in Logic Array Blocks (LABs), a programmable interconnect switch matrix, 64 bidirectional I/O pins, 7 dedicated clock/input pins, and a 33 ns pin-to-pin delay (the “-20” speed grade). The device is built on a CMOS EEPROM technology that delivers deterministic propagation delay regardless of logic utilization, which is critical for synchronous designs. Architecturally, the EPM5192 integrates the AND/OR array with output macrocells that contain programmable flip-flops, making it well suited for both combinatorial and registered designs. The UV window enables up to thousands of erase/reprogram cycles during development, although the part is one-time-programmable once the window label is removed for production. Typical applications include glue logic for legacy 5 V microprocessor and DSP systems, bus-interface and address-decoding logic, peripheral controllers in industrial control, and replacement of multiple 74-series TTL/CMOS gates in compact boards. Designers of long-life industrial and military systems also rely on this part for its deterministic timing and field-proven reliability. Designers should plan a 10–15 percent I/O and macrocell margin, use Altera MAX+PLUS II or Quartus for design entry, and budget for the UV-erase cycle (~30 minutes under a 12,000 uW/cm² lamp) if iterative prototyping is required. The 84-pin J-lead PLCC accepts standard socket or surface-mount footprints, easing both production and rework.
EPM5192AJI84-15 - 192-Macrocell UV PLD, 15ns | Altera
The Altera EPM5192AJI84-15 is a UV-erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 EPLD family, featuring 192 macrocells, 84 user I/O pins, and a propagation delay of 15 ns, housed in an 84-pin J-lead ceramic (JLCC) package. This CMOS device operates from a nominal 5 V supply (4.5 V to 5.5 V) and supports high-density glue-logic integration for legacy and industrial systems. A Programmable Logic Device (PLD) is a class of digital integrated circuit whose logic function and interconnect are defined by on-chip programmable fuses, anti-fuses, or floating-gate memory cells rather than at the mask level. In the broader system hierarchy, PLDs sit between discrete TTL/CMOS glue logic and mask-programmed gate arrays: they offer higher integration than 74-series logic, lower NRE cost than full ASICs, and faster iteration cycles than mask-programmed gate arrays. The MAX 5000 family's UV-erasable windowed package made it a 1990s workhorse for prototyping and low-volume production. Key features of the EPM5192AJI84-15 include 192 macrocells organized as 16 Logic Array Blocks (LABs) of 16 macrocells each, 84 bi-directional I/O pins, a 15 ns pin-to-pin propagation delay (tPD) enabling 50 MHz+ state-machine operation, and an internal 5 V CMOS EPROM process technology. The 'J' suffix indicates the JLCC (J-Leaded Ceramic Chip Carrier) windowed package, and 'I' designates the industrial operating temperature range of -40 °C to +85 °C. The architecture combines a global programmable interconnect array with LAB-local routing, allowing efficient implementation of wide combinational and registered logic functions such as address decoders, bus arbitrators, state machines, and peripheral controllers. The 84-pin JLCC package with quartz window supports UV erasure for re-programming during development, after which the device is typically windowed-over or replaced with the OTP 'C' (plastic) variant for production. Typical applications include legacy 5 V system glue logic, industrial control and instrumentation, military and aerospace prototyping (where MIL-STD-883 variants exist), telecom backplane controllers, and field-replaceable logic modules. The wide 5 V supply tolerance and high I/O count make it well-suited to bus-interface and address-decoding tasks in 8-/16-bit microprocessor systems. When designing with this part, verify that downstream tooling (MAX+PLUS II baseline or legacy Altera designers) is available, since modern Quartus Prime does not support the MAX 5000 family. Decoupling per MAX 5000 reference designs and respect for the UV-erase programming sequence are essential for first-time-programming success. This page synthesizes distributor pricing, pin-compatible MAX 5000 family alternatives, and practical migration notes not consolidated in any single legacy datasheet, helping engineers source and qualify obsolete Altera EPLDs.
EPM5192AJI84-20 - 192-Macrocell UV EPLD, 33ns | Altera MAX 5000
The Altera EPM5192AJI84-20 is a UV-erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 family, delivering 192 macrocells in an 84-pin ceramic J-leaded chip carrier (PLCC-84, package code JI) with a 33ns propagation delay and 66.7 MHz maximum clock frequency. This CMOS device operates from a nominal 5 V supply across a 4.5 V to 5.5 V range, suiting legacy 5 V logic designs that require high integration without an FPGA-grade architecture. A Programmable Logic Device (PLD) is a class of digital integrated circuit that allows engineers to implement custom combinational and sequential logic by configuring on-chip macrocells, instead of committing to a fixed ASIC. The hierarchy is PLD -> Complex PLD (CPLD) -> MAX-class EPLD -> programmable logic -> digital IC. The MAX 5000 family in particular pioneered UV-erasable, high-density logic with EEPROM-style macrocells, targeting glue-logic, bus interfacing, and state-machine consolidation that previously consumed multiple SSI/MSI packages. Key features of the EPM5192AJI84-20 include 192 macrocells, 33 ns pin-to-pin propagation delay (tPD), 66.7 MHz maximum frequency (fCNT), and a wide 5 V supply tolerance of 4.5 V to 5.5 V. The device is offered in the industrial temperature grade and is packaged in an 84-pin J-bend ceramic chip carrier, identified in the JEDEC code as WQCCJ. As a UV-erasable part, the device can be reprogrammed after package-window UV exposure, which made it useful for prototyping where design revisions were anticipated. Architecturally, the EPM5192AJI84-20 uses Altera's Classic macrocell with a programmable AND/OR array feeding a configurable flip-flop. Logic is compiled into sum-of-products form and routed through the Labyrinth interconnect, which balances pin-assignment flexibility against timing predictability. Because every path traverses the same global interconnect, propagation delay is essentially independent of logic placement, simplifying static timing analysis on 33 ns designs. Typical applications include 5 V TTL/CMOS glue logic, address decoding and bus arbitration for Intel 80-series and Motorola 68k microprocessors, peripheral interface controllers (GPIB, SCSI, UART), industrial state machines, and pin-compatible replacement of discrete 74LS/74F logic. Designers also used the EPM5192AJI84-20 as a single-chip replacement for multiple PAL/GAL devices in long-life-cycle industrial systems. When designing with the EPM5192AJI84-20, plan the logic to fit within 192 macrocells before compile; over-mapping typically requires stepping down to a smaller member of the MAX 5000 family. UV erasure requires a 12,000 uW-sec/cm^2 dose, so production systems usually migrate to one-time-programmable (OTP) MAX 7000/MAX 3000 successors for un-windowed packages. This page synthesizes distributor stock, J-bend footprint notes, MAX 5000 family cross-references, and practical design notes not consolidated in the original Altera datasheet, supporting engineers maintaining legacy 5 V platforms through 2026.
EPM5192AJM84-15 - 192-Macrocell UV PLD MAX 5000 | Altera
The Altera EPM5192AJM84-15 is a 192-macrocell UV-erasable programmable logic device (PLD) from the classic Altera MAX 5000 family, supplied in an 84-pin ceramic J-lead (JM84) package. The -15 speed grade corresponds to a 15 ns pin-to-pin propagation delay, supporting a maximum clock frequency of 83.3 MHz. Built on a 5 V CMOS EPROM-style architecture, the EPM5192AJM84-15 provides high-density combinatorial and registered logic with non-volatile configuration that can be erased by exposure to ultraviolet light and re-programmed many times. A Programmable Logic Device (PLD) is a class of digital integrated circuit whose internal logic array and interconnects are defined by the user after manufacture, replacing dozens of discrete TTL/CMOS glue-logic packages. The MAX 5000 family sits in the hierarchy as a high-density PLD, above simple PAL/GAL devices but below modern FPGA architectures, optimized for state-machine, bus-interface, address-decoding and peripheral-control applications. The 192-macrocell capacity of the EPM5192 places it in the upper tier of the MAX 5000 lineup, second only to the EPM5192A-family devices with the same density. Key features of the EPM5192AJM84-15 include 192 logic macrocells, 84 user I/O pins routed through the JM84 J-lead ceramic package, 15 ns propagation delay, 83.3 MHz maximum operating frequency, and a -55C to +125C military-grade operating temperature range (the 'JM' suffix denotes the JAN/MIL ceramic J-lead variant). The device is supplied as a windowed ceramic package for laboratory, aerospace, and defense applications where the ability to erase and re-program the configuration memory in-circuit or via UV exposure is required for design iteration or field upgrades. The MAX 5000 architecture uses a programmable AND/OR array with a fixed-OR, programmable-macrocell output stage; each macrocell can be configured as a D-flip-flop, T-flip-flop, or pure combinatorial output. The I/O structure is JTAG-friendly, with input registers, I/O registers, and buried registers available to absorb pipelined designs without sacrificing pin count. The chip is supported by the Altera MAX+PLUS II development environment for design entry, fitting, simulation, and programming. Typical applications for the EPM5192AJM84-15 include military and aerospace control systems, industrial bus-interface logic, address decoding for legacy processor boards, DRAM/PCI bus controllers, and other high-reliability systems requiring high-density PLD logic. The ceramic JM84 package also makes the part well suited to defense programs where MIL-PRF-38535-qualified parts are required. When designing with the EPM5192AJM84-15, allow generous decoupling (100 nF ceramic at every VCC/ground pair), follow standard CMOS anti-static handling during UV erasure, and verify timing margins against the 15 ns tPD specification across process and temperature corners. The 5 V TTL-compatible I/O simplifies interface to legacy logic but requires bus-termination discipline to avoid undershoot on long traces. This page synthesizes Altera MAX 5000 datasheet specifications, drop-in same-family alternatives, ceramic-package design considerations, and a parametric comparison versus the EPM5192A pin-compatible variants not typically collected in a single place on the manufacturer datasheet.
EPM5192AJM84-20 - 192-Macrocell UV PLD, CQFP-84 | Altera
The Altera EPM5192AJM84-20 is a CMOS UV-erasable/OTP Complex Programmable Logic Device (PLD) from the MAX 5000 family, delivering 192 macrocells organized into 12 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Housed in an 84-terminal Ceramic Quad Flat Pack (CQFP) with J-leads, this MIL-grade variant operates at a maximum clock frequency of 66.7 MHz with a propagation delay of 33 ns. A Complex Programmable Logic Device (CPLD) is a non-volatile, reprogrammable semiconductor that combines multiple PAL-like macrocell blocks on a single die, connected through a centralized interconnect matrix. PLDs sit in the programmable-logic hierarchy below FPGAs but above discrete glue logic, providing deterministic timing, instant-on behavior, and high drive strength for bus interface, state-machine, and decoder applications. Key features of the EPM5192AJM84-20 include 64 user I/O lines, 7 dedicated inputs, a maximum toggle frequency of 66.7 MHz, a pin-to-pin logic delay of 33 ns via -20 speed grade, and an extended operating temperature range suitable for military applications. The architecture uses EPROM/UV-erasable cells, allowing field reprogramming after package-window UV exposure. The device is built on a CMOS EEPROM process with Altera's classic MAX architecture, in which each LAB contains 16 macrocells feeding the PIA. This delivers fast, predictable combinatorial and registered logic with no hidden routing delays. The JEDEC S-CQCC-J84 CQFP package provides hermetic sealing for harsh-environment deployment, with a windowed ceramic lid enabling UV erasure. Typical applications include military and aerospace control logic, radiation-tolerant interface glue, legacy bus-arbiter replacement, vintage telecommunications backplanes, and industrial test equipment requiring MIL-spec plastic alternatives. The CQFP-84 footprint is also well-suited for retrofit boards originally designed around MAX 5000-series devices. When designing, allocate a UV erasure window budget: quartz-windowed ceramic packages must be erased with 12,000 uW-s/cm² of UV-C (253.7 nm) before reprogramming, and OTP variants cannot be re-programmed. The MIL temperature grade and hermetic CQFP package require careful PCB footprint matching to the 84-pin J-lead land pattern. This page synthesizes distributor stock, MIL-grade variant listings, and drop-in replacement guidance for legacy MAX 5000 designs not consolidated on any single distributor page.
EPM5192ALC84-15 - 192-Macrocell MAX 5000 EPLD, 15ns | Altera
The Altera EPM5192ALC84-15 is a UV-erasable / OTP Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 192 macrocells, 64 user I/O pins, and a 15 ns pin-to-pin propagation delay. Implemented in a 5 V CMOS process, it operates from a 4.75 V to 5.25 V supply and is housed in an 84-pin ceramic J-lead chip carrier (PLCC-84). According to the MAX 5000 datasheet family, the device integrates a programmable AND/OR/INVERT logic array with macrocell registers and a deterministic interconnect, enabling designers to replace 20-plus discrete SSI/MSI packages with a single non-volatile logic solution. What is a Complex PLD (CPLD)? A CPLD is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell blocks on one die with a centralized programmable interconnect matrix (PIA). CPLDs sit between discrete gate arrays and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> programmable logic -> semiconductor. Their key advantages are deterministic timing, instant (zero-power) power-on, and excellent pin-to-pin compatibility across speed grades. Key features of the EPM5192ALC84-15 include 7 dedicated inputs feeding a high-drive bus, 192 macrocells (each with a flip-flop and product-term allocation), 64 bidirectional I/O pins with 5 V tolerant interfaces, and a 15 ns combinatorial propagation delay at 5 V. Built on the mature EPROM-based MAX 5000 architecture, it offers one-time-programmable (OTP) or UV-erasable behavior with no configuration memory required. The MAX 5000 architecture places logic signals through a Programmable Interconnect Array (PIA) that guarantees a fixed, predictable delay independent of the routed path. This contrasts with SRAM-based FPGAs whose routing delays are data-dependent, making the EPM5192ALC84-15 a strong fit for fast control and decode functions where timing closure is critical. Typical applications include bus-address decoding and glue logic in VME/PCI/ISA backplanes, high-speed state-machine controllers, peripheral-interface adapters for motor drives, military/aerospace systems (per MIL-STD-883C processing on the ceramic QCCJ package), and replacement of multi-gate SSI/MSI logic in long-lifecycle industrial designs. When designing with this device, allocate product terms per macrocell carefully: the 192-macrocell budget must cover both combinatorial and registered functions. Use the MAX+PLUS II or Altera Classic development toolchain for design entry, fitting, and JEDEC file generation. Decoupling: place one 0.1 uF ceramic bypass capacitor per VCC/VCCIO pair within 5 mm of each pin cluster. This page consolidates distributor stock, drop-in equivalents, and practical layout notes not always present in the manufacturer datasheet, including pin-compatible MAX 5000 speed/pinout variants and modern cross-brand guidance.
EPM5192ALC84-20 - Altera 192-Macrocell MAX 5000 EPLD | PLCC-84
The Altera EPM5192ALC84-20 is a UV-Erasable/OTP Complex Programmable Logic Device (CPLD/EPLD) from the high-speed, high-density MAX 5000 family, integrating 192 macrocells in an 84-terminal Plastic Leaded Chip Carrier (PLCC-84) package with J-bend terminals on a 1.270 mm pitch and a commercial temperature grading. It is implemented in CMOS technology, drawing its architectural heritage from the Altera MAX series that defined the early-to-mid 1990s high-density programmable logic market, and is specified with the "-20" speed grade indicating a worst-case pin-to-pin logic delay of 20 ns. A Complex PLD (CPLD) is a non-volatile, electrically programmable logic device that contains an array of AND/OR macrocell logic blocks interconnected by a global programmable interconnect matrix. In the system hierarchy, the CPLD sits between discrete SSI/MSI logic (gates, flip-flops) and the more recent SRAM-based FPGA; the EPM5192 specifically belongs to the EPLD subcategory (Erasable Programmable Logic Device), where configuration is stored in EPROM cells that can be erased only by UV exposure through a quartz window - a hallmark of the MAX 5000 era. This makes the part well-suited to production volumes where bitstream security and one-time-programmability are valued over in-field re-programmability. Key features include 192 macrocells of user logic, the 20 ns pin-to-pin combinatorial delay (-20 speed grade), a CMOS process with TTL-compatible I/O, and the plastic J-lead PLCC-84 footprint that allows low-cost socket programming and field replacement. The MAX 5000 architecture integrates multiple Logic Array Blocks (LABs) with a centralized interconnect, providing deterministic timing that CPLDs are valued for - in contrast to the statistical routing delays of SRAM FPGAs, every EPM5192 signal path has a guaranteed worst-case delay. Typical applications include legacy industrial control logic, glue logic replacement for vintage PC/AT motherboards and embedded controller boards, address decoding and bus interface logic, motor and stepper driver sequencing, and any design that was originally specified around a MAX 5000 series EPLD in the 1990s. Engineers maintaining long-life industrial and military platforms still depend on this part because the original design documentation, board layout, and timing closure were all done against the EPM5192 - substituting an unrelated CPLD family would require re-validating timing across every signal path. When designing with this device, designers should note that the device is non-volatile only after EPROM programming, so any change requires UV erasure and reprogramming; modern JTAG-based ISP is not available on MAX 5000. For new designs, designers should evaluate whether a current-generation MAX II or MAX V CPLD (in a different package and pinout) offers better migration economics rather than specifying this mature legacy part. This page synthesizes distributor pricing, a parametric comparison against pin-compatible MAX 5000 variants, and practical design notes not found in the manufacturer datasheet - information engineered to help buyers and legacy-system maintainers source and qualify the EPM5192ALC84-20 with confidence.
EPM5192ALI84-15 - 192-Macrocell OTP PLD, 84-PQCC | Altera
The Altera EPM5192ALI84-15 is a 192-macrocell, CMOS, One-Time Programmable (OTP) Complex Programmable Logic Device (PLD) from the MAX 5000 family, housed in an 84-pin Plastic Quad Chip Carrier (PQCC / PLCC, JEDEC JESD-30 code S-PQCC-J84) package. It features a propagation delay of 25 ns (the "-15" speed grade) and is qualified to industrial temperature range, providing high-density glue-logic integration for legacy through-hole and socketed designs. A Complex PLD (CPLD predecessor) is a non-volatile programmable logic device that combines multiple AND/OR macrocell arrays on a single die. The EPM5192 belongs to the MAX 5000 family - Altera's high-density, high-speed, UV-erasable/OTP CMOS PLD series positioned between classic PAL/GAL devices and modern MAX II CPLDs. Within the broader programmable logic taxonomy, this device sits in the hierarchy: macrocell-based PLD -> MAX 5000 family -> UV-erasable/OTP Complex PLD -> programmable logic -> semiconductor IC. Key features of the EPM5192ALI84-15 include 192 logic macrocells, 7 dedicated input pins, 64 bidirectional I/O pins supporting up to 72 total input channels, propagation delay tPD of 25 ns (-15 speed grade), and CMOS non-volatile OTP programming via on-chip EPROM cells. The device is offered in industrial grade (-40C to +85C). The PQCC J-Lead package (JESD-30 S-PQCC-J84) is socket-compatible with standard PLCC-84 sockets, easing field replacement and programming-socket tooling. Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding and wait-state generation in 8/16/20 MHz microprocessor systems, replacement of discrete 7400-series TTL glue, and high-pin-count state-machine integration in through-hole assembly lines where modern BGA/QFP CPLDs are not pin-compatible. The OTP architecture is suitable for production-volume designs where design changes are infrequent. Design consideration: confirm availability of compatible 84-pin PLCC programming sockets before PCB layout commit; modern CPLDs in fine-pitch QFP/BGA do NOT drop in. For new designs, consider MAX II or MAX V CPLDs as a migration path only if PCB layout can be changed. This page synthesizes EPM5192ALI84-15 distributor availability, package/die siblings, and field-replacement guidance not consolidated on the manufacturer datasheet.
EPM5192ALI84-20 - 192-Macrocell MAX 5000 PLD, 84-Pin J-Lead | Altera
The Altera EPM5192ALI84-20 is a high-density CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, integrating 192 macrocells into an 84-pin Plastic Leaded Chip Carrier (PLCC / QCCJ) J-bend package. It is built on Altera's classic UV-erasable / one-time-programmable EPROM-based architecture with a 20 ns propagation delay pin, making it a long-standing workhorse for glue-logic, bus decoding, and state-machine integration in legacy industrial, telecom, and military systems. Operating from a single 5 V supply with TTL-compatible I/O, the device combines the density of a small CPLD with the timing predictability of an OTP logic array. What is a MAX 5000 PLD? The MAX (Multiple Array matriX) 5000 family is Altera's second-generation EPLD product line. A PLD (Programmable Logic Device) sits in the broader hierarchy of programmable logic: PLD -> EPLD/CPLD -> programmable logic -> digital semiconductor. Unlike SRAM-based FPGAs, the MAX 5000 series uses non-volatile EPROM cells to retain configuration, which means designs persist without external boot memory and are inherently more secure against bitstream readback. Key features include 192 macrocells organized in logic array blocks (LABs), 84 user I/O pins (the maximum available in this package), a maximum propagation delay of 20 ns (the "-20" speed grade), industrial operating temperature grading (the "I" suffix), and TTL-compatible inputs and outputs. The device supports both combinatorial and registered logic with per-macrocell flip-flops, and offers global clock networks with programmable polarity. The MAX 5000 architecture uses a programmable AND/OR array with EPROM storage elements and a fixed interconnect matrix. Each macrocell contains a flip-flop, a programmable clock, and feedback paths into the LAB, allowing implementation of registered functions, counters, and finite state machines. With 192 macrocells the EPM5192 typically delivers equivalent gates in the 5000-7500 range, with deterministic tPD/tCO timing that aids static timing closure without synthesis-time retiming. Typical applications include 5V TTL/CMOS glue logic for legacy microprocessor and DSP buses, address decoding and chip-select generation, bus arbitration and protocol translation, state-machine controllers for industrial automation, and embedded control subsystems on VME, ISA, or PC/104 boards. The plastic J-leaded PLCC package also supports socketed programming and field replacement, useful in long-lifecycle industrial equipment. When designing with this part, note that the EPM5192 series is a member of Altera's classic MAX 5000 family and is now considered legacy/obsolete technology for new designs. Most long-life applications use the JTAG/ISP variants; the EPM5192A series is UV-erasable or one-time-programmable only. New designs should target MAX II or MAX V CPLDs for ISP support, lower power, and modern I/O standards. This page synthesizes distributor availability, package-level drop-in alternatives from Altera's MAX 5000 family, and practical design notes for long-life maintenance scenarios not found in the original Altera datasheet.
EPM5192ALM84-15 - 192-Macrocell OTP PLD, 15ns, 84-PLCC | Altera
The Altera EPM5192ALM84-15 is an OTP (One-Time Programmable) Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 192 macrocells and housed in an 84-pin PLCC (J-lead, square) package with military temperature grading. The device operates from a single 5V supply (4.5V to 5.5V) and is fabricated in CMOS technology for low power consumption. It offers a 15ns propagation delay (note: verified web data lists 25ns; -15 speed grade in the part suffix indicates the tPD speed bin per Altera MAX 5000 ordering conventions). A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of PAL/GAL with higher logic density, typically containing multiple logic blocks with macrocells, a programmable interconnect matrix, and I/O blocks. CPLDs sit between simple SPLDs (PAL/GAL) and FPGAs in the programmable logic hierarchy, offering instant-on behavior (no boot loader), deterministic timing, and high-drive outputs - making them well-suited for glue logic, bus interfacing, address decoding, and state-machine replacement in legacy designs. The MAX 5000 series was Altera's classic high-density CPLD family, succeeded by MAX 7000 and MAX II/MAX V. Key features of the EPM5192ALM84-15 include 192 macrocells (high logic density for the era), CMOS process technology, J-lead (J-bend) PLCC package for through-hole or socket mounting, and a maximum internal clock frequency up to 83.3 MHz. The device is windowless/OTP - meaning programming is permanent (one-time) - versus the older erasable UV-windowed variants. Military temperature grade enables operation across extended environmental ranges. Typical applications include address decoding and bus interfacing in 5V systems, glue logic replacement, state machine implementation, and legacy 5V logic consolidation in industrial, telecom, and military systems where the MAX 5000 footprint is already designed in. Note that EPM5192 series parts are legacy/obsolete in current Altera (Intel FPGA) catalogs. When designing with this part, verify the exact speed grade against your timing requirements (the '-15' suffix in the part number designates the Altera MAX 5000 tPD bin). The PLCC-84 socket footprint enables easy prototyping and replacement, and the OTP nature means security fuses are not required for IP protection - the program cannot be read back. This page synthesizes distributor availability, cross-reference alternatives from the same MAX 5000 family, and design considerations specific to the 84-pin PLCC package that are not consolidated in the manufacturer datasheet alone.