FPGA & CPLD
Products (6,800+)
EPM5064LC-2 - 64-Macrocell MAX 5000 CPLD, 45ns, PLCC44 | Altera
The Altera EPM5064LC-2 is a 64-macrocell CMOS Erasable Programmable Logic Device (EPLD) from the legacy MAX 5000 family, supplied in a 44-pin PLCC (J-Lead) package. It provides 64 macrocells, 36 input lines (7 dedicated inputs plus 28 I/O lines), 28 output functions / flip-flops, and a propagation delay of 45 ns with a maximum clock frequency of 40 MHz. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays on a single die with a programmable interconnect matrix. The MAX 5000 architecture uses CMOS EPROM / UV-erasable cells (OTP variants denoted "LC" use one-time-programmable EPROM) to retain the configuration without a separate boot memory. CPLDs sit in the broader hierarchy of programmable logic: simple PLD (PAL/GAL) -> CPLD -> FPGA, and are preferred over FPGAs when deterministic pin-to-pin timing, instant-on behavior, and a small fixed logic capacity are sufficient. Key features of the EPM5064LC-2 include: 64 macrocells, 36 inputs, 28 I/O pins, 4 logic array blocks (LABs) each containing 16 macrocells, 45 ns combinational propagation delay (tPD), 40 MHz maximum internal frequency, and a programmable AND/OR array with per-macrocell flip-flop (D/T/JK/SR). Programming is performed via a JTAG-compatible or Altera-proprietary byte-wide programmer, and the device is OTP (one-time programmable) in the LC variant. Typical applications include legacy glue-logic replacement, address decoding and bus-interface adaptation, state-machine controllers in industrial control boards, and pin-compatible second-source designs for MAX 5000 sockets. The LC-2 speed grade is one bin slower than LC-1 and is often chosen where timing margin is acceptable and lower-cost / wider-availability parts are preferred. When designing with the EPM5064LC-2, plan for 4.75 V to 5.25 V single-supply operation, add 0.1 uF + 1 uF decoupling near each VCC/ GND pair, and verify timing with Altera MAX+PLUS II timing analysis. Confirm second-source availability before committing to the LC OTP process flow. This page consolidates distributor pricing, drop-in same-package alternatives, and design notes for engineers maintaining MAX 5000 designs — context not present in the original datasheet PDF.
EPM5064LI - 64-Macrocell MAX 5000 CPLD, 5V, PLCC-44 | Altera
The Altera EPM5064LI is a UV-erasable/OTP Complex Programmable Logic Device (CPLD) from the classic MAX 5000 family, delivering 64 macrocells organized across 4 interconnected Logic Array Blocks (LABs). The device is housed in a 44-terminal Plastic J-Leaded Chip Carrier package (PLCC-44, package code QCCJ) and operates from a single 4.5V to 5.5V supply. Maximum clock frequency is rated at 33.3 MHz with a typical propagation delay of 55 ns, and the part provides 28 bidirectional I/O pins plus 7 dedicated inputs for a total of 36 usable inputs. According to the MAX 5000 datasheet, this CMOS device is built on a 1-micron EPIC process with 500-mA typical latch-up immunity at 125C. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the hierarchy between simple PAL/GAL devices and high-density FPGAs. CPLDs typically contain multiple macrocells with sum-of-products logic and a centralized interconnect fabric, providing fast, deterministic pin-to-pin propagation delays ideal for glue logic, bus decoding, and state-machine implementation. The MAX 5000 family was among the earliest commercially successful CPLD families, combining EPROM/EEPROM non-volatile configuration with predictable timing — a useful baseline for legacy industrial and telecom designs. Key features of the EPM5064LI include 64 macrocells, 4 LABs, 28 I/O pins, 7 dedicated inputs, 33.3 MHz maximum frequency, 55 ns propagation delay, 4.5V to 5.5V single-supply operation, industrial temperature grading, and J-bend PLCC-44 terminals. The non-volatile UV-erasable (windowed) or one-time-programmable (OTP) configuration memory eliminates the need for an external boot PROM and ensures instant-on behavior on power-up. The MAX architecture provides 100% interconnect within and between LABs. Technically, the EPM5064LI uses Altera's classic MAX architecture in which each macrocell contains a programmable AND/OR array feeding a configurable flip-flop with product-term steering. The 4 LABs share a global interconnect that provides 100% connectivity between any two macrocells, enabling highly flexible logic placement. The I/O structure is symmetrical, with 28 bidirectional pins that can be configured for input, output, or tri-state operation with independent output enable control. Typical applications include legacy industrial control glue logic, address decoding for microprocessor systems, bus interface and protocol bridging, state-machine controllers, and replacement of discrete TTL/CMOS logic in long-life-cycle equipment. The industrial temperature grade makes the part suitable for factory automation and outdoor control cabinets. When designing with this device, engineers should plan for the 55 ns propagation delay when computing critical timing margins and confirm the 5V supply requirement is compatible with surrounding logic. The PLCC-44 socket footprint simplifies prototyping and field replacement, which is important for legacy systems still in production. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM5128GC - 128-Macrocell MAX 5000 CPLD | Altera | 68-Pin PGA
The Altera EPM5128GC is a high-speed, high-density CMOS EPLD from the MAX 5000 family, providing 128 macrocells and approximately 2,500 usable gates in a 68-pin ceramic PGA with windowed (erasable UV) package. It is built on Altera's classic MAX architecture, which uses a programmable AND/OR array with a fixed OR plane, and operates from a single 5V supply at commercial temperature grades. Per the manufacturer datasheet, the EPM5128GC is the standard (non-speed-graded) variant of the family; the -1 suffix denotes a power/performance option, while the GC suffix denotes the ceramic windowed PGA package for prototyping and lab use. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC containing multiple PLD-like macrocell blocks interconnected by a central programmable interconnect matrix. CPLDs sit between small PAL/GAL devices and large FPGAs, offering deterministic pin-to-pin propagation delays, instant-on configuration (no boot flash needed), and high pin-to-gate density for glue-logic, address decoding, bus interface, and state-machine applications. Key features of the EPM5128GC include 128 macrocells organized in multiple Logic Array Blocks (LABs), 68 user I/O pins on the ceramic PGA package, and Altera's programmable I/O architecture supporting TTL and CMOS interface levels. The device supports user-programmable security bits and is in-system UV-erasable, making it well suited to engineering development environments where design iteration is expected. The MAX 5000 architecture uses a CMOS EEPROM-based configuration cell, so the device retains its logic pattern with no external boot PROM. The fixed interconnect provides predictable, consistent timing across operating conditions - a key advantage over SRAM-based FPGAs. With 128 macrocells, the EPM5128GC can implement substantial state machines, multi-channel address decoders, or peripheral bus bridges in a single chip. Typical applications include prototyping and design iteration of glue-logic designs, replacement of multiple discrete PAL/GAL devices, industrial bus-interface bridging (ISA, parallel port, custom), and educational platforms where UV erasure allows multiple programming cycles. The ceramic PGA package also makes the part useful for laboratory test fixtures and reference designs. When designing with the EPM5128GC, engineers should provide a clean 5V rail and respect the I/O pin count of 68, configure the device using MAX+PLUS II or the legacy Altera programming toolchain, and note that ceramic PGA sockets are required to allow UV erasure. For new designs, designers should consider the modern MAX II/MAX V equivalents in surface-mount packages. This page synthesizes distributor availability, parametric alternatives from the same MAX family, and practical design notes not found in the original manufacturer datasheet.
EPM5128GC-1 - 128-Macrocell CPLD, 62.5MHz, 5V MAX 5000 | Altera
The Altera EPM5128GC-1 is a UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the classic MAX 5000 family, integrating 128 macrocells, 2.5K usable gates, and 7 dedicated inputs with up to 52 usable I/O pins in a PGA-96+ ceramic windowed package. It operates from a single 5 V nominal supply (4.75 V to 5.25 V), supports tPD propagation delays as low as 16 ns, and reaches a maximum clock frequency of 62.5 MHz (with the -1 speed grade). A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic IC that combines multiple PAL-style macrocell blocks with a central programmable interconnect matrix. In the system hierarchy it sits between simple SPLDs/GALs and larger FPGAs, offering predictable timing, deterministic logic implementation, and instant boot without external configuration memory. CPLDs are widely used as glue logic, bus-interface bridges, and state-machine controllers in industrial, telecom, and embedded designs where low power, fast propagation, and rugged pin-for-pin replacement behavior are required. Key features of the EPM5128GC-1 include 128 macrocells with 100% connectivity, 4.75-5.25 V single-supply operation, 100 mA IOL/25 mA IOH drive capability per pin, JTAG-compatible in-system programming on selected packages, and a programmable security bit for logic protection. The device supports both combinatorial and registered logic with per-macrocell flip-flops, and offers low-power CMOS technology with typical standby currents in the milliamp range. The ceramic PGA-96+ package includes an erasable quartz window for prototype or development reuse via UV erasure. Internally the EPM5128GC-1 is organized as multiple Logic Array Blocks (LABs) connected by the Programmable Interconnect Array (PIA). Each macrocell contains an AND/OR array with expander-product support, a programmable flip-flop, and an I/O control block that can be configured as input, output, or bidirectional. This architecture delivers deterministic, pin-locked timing - a defining MAX 5000 trait - which simplifies timing closure compared with SRAM-based FPGAs. Typical applications include address decoding and bus-interface glue logic in legacy 5V microcontroller and microprocessor systems, programmable state machines for industrial control, peripheral controllers (UART, timer, PWM), and replacement of multiple discrete 74LS/74HC TTL devices with a single reconfigurable part. The 5V tolerant I/O makes it ideal for retrofitting older 5V-only boards where 3.3V-only modern CPLDs cannot be used. When designing with the EPM5128GC-1, engineers should verify that the chosen package pinout matches the Altera MAX 5000 datasheet PGA-96+ pin map, add proper 0.1 uF decoupling on every supply pin, and use the Altera MAX+PLUS II or Quartus legacy support for design entry. Designers should also note that the ceramic windowed package is intended primarily for development - production boards typically migrate to the plastic-windowless equivalent for cost. This page synthesizes distributor pricing for EPM5128GC-1, same-family drop-in alternatives, parametric comparisons, and practical design notes that go beyond what the legacy Altera MAX 5000 datasheet alone provides.
EPM5128GC-2 - 128-Macrocell MAX 5000 CPLD, 50MHz, 5V | Altera
The Altera EPM5128GC-2 is a high-density, high-speed CMOS Erasable Programmable Logic Device (EPLD) from the legacy MAX 5000 family, integrating 2,500 usable gates and 128 macrocells in a single 68-pin PGA (Pin Grid Array) package. It operates with a 5V core supply and supports in-system propagation delays consistent with the -2 speed grade (tPD approximately 25 ns and a maximum toggle frequency near 50 MHz), making it suitable for glue-logic and state-machine replacement on 5V-tolerant boards. The MAX 5000 architecture combines EPROM-based configuration memory with a programmable AND/OR array, allowing designers to combine multiple SSI/MSI functions into a single device while retaining one-time programmable non-volatile storage. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that bridges the gap between discrete 74-series glue logic and larger FPGAs, integrating PAL/GAL-like macrocells with a wide AND-OR logic plane to implement combinational and registered logic. The MAX 5000 family uses ultraviolet-erasable EPROM cells for configuration and is considered a predecessor of the modern MAX 7000/MAX II families; it sits within the broader hierarchy of programmable logic devices (PLDs) -> CPLDs -> non-volatile logic ICs -> digital semiconductors. Key features include 2,500 gates, 128 macrocells, 68 programmable I/O pins, an enhanced -2 speed grade, and a 5V VCC tolerance suitable for legacy TTL/CMOS interfaces. Designers value the deterministic timing, low power consumption, and one-time programmable security for production designs. Technically, the EPM5128GC-2 leverages Altera's classic MAX architecture with buried macrocells and a programmable interconnect array (PIA) that routes sum-of-products terms across the device. Configuration is stored in UV-erasable EPROM cells, so the device is one-time programmable in production and erasable only with quartz-window exposure. Operating junction temperature spans 0C to +70C (commercial grade), and the ceramic PGA package (GC suffix) offers robust thermal performance for through-hole or socketed mounting. Typical applications include industrial 5V bus interface glue logic, legacy peripheral controllers (e.g., address decoding for ISA/VME), state-machine replacement in motor control, and retrofit designs that must match existing 5V CPLD footprints. It is also widely used in educational kits and aerospace/military programs where Altera's MAX 5000 silicon remains a long-lifecycle part. Designers should note that the EPM5128GC-2 requires a 5V supply rail and is not 3.3V tolerant; I/O banks share the VCC supply, so mixed-voltage interfacing demands external level shifters. For new designs, modern MAX II or MAX V equivalents in surface-mount packages are recommended, but the EPM5128GC-2 remains invaluable for maintenance and lifecycle-extension of legacy boards. This page synthesizes distributor pricing, same-brand MAX 5000 alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers evaluate the EPM5128GC-2 for both legacy support and cost-down retrofits.
EPM5128GC2 - MAX 5000 CPLD 128 Macro Cells 50MHz 5V | Altera
The Altera (Intel) EPM5128GC2 is a member of the classic MAX 5000 family of high-speed, high-density CMOS Erasable Programmable Logic Devices (EPLDs) with 128 macro cells, 2.5K usable gates, a 50 MHz internal frequency, and 5V core supply, offered in a ceramic PGA package designated GC. The "GC" package code denotes a ceramic Pin Grid Array with a windowed (erasable) lid suitable for development, prototyping, and reprogrammable production flows. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of a PAL (Programmable Array Logic) with an EPROM-style erasable cell, allowing engineers to implement glue logic, state machines, address decoding, bus interfacing, and other random-logic functions in a single chip. Within the broader programmable logic hierarchy, EPLDs sit between simple SPLDs/PALs and higher-density CPLDs and FPGAs, offering predictable timing, instant-on behavior, and zero in-system configuration overhead because the logic is stored in on-chip EPROM cells. Key features of the EPM5128GC2 include 128 macro cells organized into 8 Logic Array Blocks (LABs) of 16 macro cells each, 16 dedicated inputs, 64 I/O pins, a programmable interconnect array (PIA), a 5V VCC supply with 5V-tolerant I/O, a maximum internal toggle frequency of 50 MHz, propagation delays measured in tens of nanoseconds, and a programmable macrocell flip-flop with selectable D/T/JK/SR behavior. Per the datasheet, the part supports both combinatorial and registered logic with dedicated clear, preset, and clock controls per macro cell. The MAX 5000 architecture uses a sum-of-products AND/OR plane feeding a programmable macrocell register, with a global PIA that routes signals between LABs. This architecture provides fast, deterministic pin-to-pin timing that is independent of logic placement, which is highly desirable for asynchronous glue logic and bus interface designs. Unlike SRAM-based FPGAs, the EPM5128GC2 holds its configuration without external boot memory and is ready to drive outputs within nanoseconds of VCC ramp. Typical applications include legacy 5V bus-interface and address-decoding logic in industrial control backplanes, prototyping adapters and test fixtures where the ceramic PGA windowed package allows UV erasure and reuse, MIL/aerospace and high-reliability systems that still require mature 5V CPLD logic, replacement of discrete 74LS/74F glue-logic gates, and as a bridge between 5V and 3.3V buses using its 5V-tolerant I/O structure. When designing with this device, the ceramic PGA windowed package requires a UV eraser for reprogramming, so high-volume production generally migrates to one-time-programmable (OTP) plastic package variants such as EPM5128LC, while the GC2 remains the preferred choice for engineering development, breadboarding, and long-life military/aerospace programs. This page synthesizes distributor inventory, same-family drop-in alternatives (EPM5128GC, EPM5128GC-1), and practical design notes that go beyond what the MAX 5000 datasheet provides in isolation.
EPM5128GI - 128-Cell UV PLD, MAX 5000, CPGA-68 | Altera
The Altera EPM5128GI is a high-density, high-speed UV-erasable Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 logic cells in a 68-pin ceramic Pin Grid Array (CPGA-68) windowed package. It offers a pin-to-pin propagation delay of 55 ns, operates from a single 5 V supply, and is designed for industrial temperature-grade applications requiring in-system reprogrammability through its UV-erasable EPROM technology. A CPLD (Complex Programmable Logic Device) is a non-volatile, factory-programmable integrated circuit that combines multiple PAL/GAL macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic taxonomy between simple SPLDs/CPLDs and larger FPGAs. CPLDs are deterministic, have predictable timing (fixed propagation delay), retain configuration without external memory, and are typically used for glue logic, bus interfacing, address decoding, and state-machine implementation. The MAX 5000 family was Altera's first-generation high-density UV-erasable CPLD family, positioned for prototyping and production designs that benefit from windowed erasure and reprogramming. Key features of the EPM5128GI include 128 macrocells, 100% factory-tested logic, 5V CMOS technology, and a ceramic windowed package that allows repeated UV erasure for prototyping iterations. The CPGA-68 ceramic package provides robust mechanical and thermal performance suitable for industrial and military-grade applications. The device is also offered in plastic OTP (one-time-programmable) variants for high-volume production where re-programmability is not required. Architecturally, the MAX 5000 family uses Altera's classic EPLD architecture with Logic Array Blocks (LABs) and a global programmable interconnect array (PIA), which provides fully deterministic, hazard-free combinatorial and registered logic. The EPROM-based configuration cell technology ensures non-volatile storage of the user's logic design with no external boot PROM required. The 55 ns propagation delay supports interfaces up to approximately 18 MHz in combinatorial paths. Typical applications include industrial control logic, address decoding and bus interfacing in legacy 5V systems, prototyping platforms where iterative UV erasure is required, glue logic for microprocessor and microcontroller peripherals, state-machine controllers, and military/aerospace systems that require a windowed, reprogrammable, hermetic ceramic package. When designing with this device, account for the CPGA-68 socket requirement (it is not surface-mountable) and verify that your programmer supports the MAX 5000 family algorithm. The 5V-only supply and 55 ns speed grade place it in legacy designs; modern 3.3V systems should consider MAX 7000 or MAX II families instead. This page synthesizes distributor pricing, datasheet links, and same-family Altera alternatives for engineers evaluating or sourcing the EPM5128GI — practical context that goes beyond the original datasheet.
EPM5128GM/883 - 128-Macrocell MAX 5000 CPLD | Altera | Military
The Intel / Altera EPM5128GM/883 is a 128-macrocell high-density erasable programmable logic device (EPLD) from the classic MAX 5000 family, qualified to MIL-STD-883 Class B for military and aerospace applications. It provides 128 macrocells and up to 100 user I/O, an industry-leading density at introduction, packaged in a ceramic Pin-Grid Array (PGA) form factor with 192 pins per the verified Altera datasheet family. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that uses a sum-of-products architecture with a global interconnect fabric to implement combinational and sequential logic. CPLDs sit in the hierarchy between simple PLDs (PALs/GALs) and SRAM-based FPGAs, providing deterministic timing, instant-on configuration from on-chip EPROM cells, and high fan-in macrocell structures. The MAX 5000 family was one of Altera's first high-density erasable CPLD lines, built on a UV-erasable CMOS EPROM process that allowed field re-programming via windowed ceramic packages. Key features of the EPM5128GM/883 include 128 macrocells with up to 5,000 usable gates, 100% factory-tested operation over the military -55C to +125C temperature range, JTAG-compliant boundary-scan test support, and programmable power management with macrocell-level clock-enable control. The 192-pin ceramic PGA package provides mechanical robustness for high-shock and high-vibration environments typical of avionics and defense electronics. Architecturally, the EPM5128GM/883 uses Altera's classic Logic Array Block (LAB) and Programmable Interconnect Array (PIA) structure, with each macrocell containing a programmable AND/OR array feeding a configurable flip-flop. Configuration data is stored in on-chip EPROM cells, enabling the part to retain its logic pattern without external memory and to be re-programmed after UV erasure through the ceramic windowed package. Typical applications include military avionics bus interfaces, radar signal preprocessing, missile guidance logic, naval combat-system glue logic, and space-grade digital control. The combination of high density, MIL-STD-883 screening, and non-volatile EPROM configuration makes the EPM5128GM/883 particularly suited to long-lifecycle defense programs where component stability and traceability outweigh the need for state-of-the-art density. Designers should note that the EPM5128GM/883 uses 5 V TTL-compatible I/O and requires a +12 V VPP programming supply during device programming; the 192-pin PGA footprint requires through-hole PCB assembly, which impacts board density and assembly cost compared to surface-mount equivalents. This page synthesizes distributor pricing, MIL-STD-883 screening details, and drop-in / same-family alternatives that go beyond what the manufacturer datasheet alone provides for legacy defense procurement.
EPM5128GM/883B - Military MAX 5000 EPLD 128 Macrocell | Altera
The Altera EPM5128GM/883B is a 128-macrocell high-density, high-speed CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, supplied in a ceramic Pin Grid Array (PGA) package and screened to MIL-STD-883 Class B for defense and aerospace applications. It provides 100% factory-tested replacements for 7400-series SSI/MSI TTL and CMOS logic while integrating up to 100 equivalent PAL/GAL devices into a single package. The device operates over the military -55C to +125C temperature range and is offered as a user-configurable, high-performance Multiple Array Matrix architecture device. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile, electrically erasable CMOS logic device that combines the integration density of gate arrays with the design flexibility of programmable logic. The MAX 5000 family sits in the hierarchy of programmable logic devices (EPLD -> PLD -> programmable logic -> digital IC -> semiconductor), bridging the gap between early PAL/GAL parts and modern FPGAs/CPLDs. EPLDs retain their configuration in on-chip non-volatile memory and require no external boot PROM, which is why they remain attractive for military and avionics applications. Key features of the EPM5128GM/883B include 128 macrocells, 16 dedicated inputs, and a propagation delay in the nanosecond range suited for high-speed bus decoding and state-machine replacement. The MAX 5000 Multiple Array Matrix (MAX) architecture combines the flexibility of macrocell-based logic with predictable, pin-locked timing - a critical property for synchronous military systems where routing-induced delay skew is unacceptable. The part is windowed ceramic and field-programmable through standard Altera programming hardware. Typical applications include military and avionics bus interface logic (1553B, ARINC 429 glue logic), radar signal pre-processing, sonar systems, missile guidance electronics, nuclear-hardened control systems, and any high-reliability design that previously relied on racks of 7400-series TTL. The MIL-STD-883B screening guarantees performance under vibration, thermal cycling, and extended temperature exposure. When designing with the EPM5128GM/883B, engineers must provide a socket for the ceramic PGA or use a compatible adapter footprint, and program the device using legacy Altera programming tools such as MAX+PLUS II. The /883B suffix indicates full Class B processing - if your system only needs industrial temperature ranges, the commercial EPM5128GM may suffice at lower cost.
EPM5128GM883B - 128-Macrocell UV EPLD MAX 5000 | Altera
The Altera EPM5128GM883B is a UV-erasable programmable logic device (EPLD) from the MAX 5000 family, featuring 128 macrocells, 52 I/O lines, 7 dedicated inputs, and a propagation delay of 55 ns, housed in a ceramic PGA-883 package and qualified to MIL-STD-883 Class B. The device is organized as 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), supports one external clock input, and operates from a single 5 V supply using CMOS technology. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines AND/OR array logic with macrocell flip-flops. EPLDs sit at the bottom of the programmable logic hierarchy: macrocell -> CPLD -> programmable logic -> digital IC. Unlike SRAM-based FPGAs that require a configuration ROM, EPLDs retain their logic on power-down and boot in microseconds, which is critical for power-on control logic and glue logic replacement. Key features of the EPM5128GM883B include 128 macrocells of user logic, 59 total inputs (52 user I/O + 7 dedicated), 8 LABs, a PIA that distributes signals between every LAB with uniform delay, and 55 ns pin-to-pin propagation delay. The MAX 5000 architecture provides predictable timing because every signal path traverses the same PIA, simplifying static timing analysis versus SRAM FPGA fabric. Technically, the EPM5128GM883B uses UV-erasable EPROM cells for configuration retention and CMOS I/O for low static power. The GM883B suffix designates a ceramic pin grid array package and MIL-STD-883 Class B processing for military and aerospace programs. The dedicated clock pin feeds a global clock network that drives every macrocell register with low skew. Typical applications include military and aerospace avionics, industrial control glue logic, bus interface adapters, state-machine controllers, and address decoding for microprocessor systems. Designers select the EPM5128GM883B when a moderate-density, non-volatile, deterministic-timing logic device is required for harsh-environment programs. When designing with this part, budget for a UV eraser window on the top of the package because the device must be exposed to UV-C light for ~20 minutes to erase. Also verify that 55 ns propagation delay meets the system timing budget; if not, consider the -2 speed grade variant with 45 ns delay.
EPM5128JC - 128-Macrocell MAX 5000 CPLD, 35ns, PLCC-68 | Altera
The Altera EPM5128JC is a 128-macrocell, high-density CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, housed in a 68-pin ceramic J-leaded PLCC package and rated for commercial operating temperature. According to the manufacturer datasheet, the device integrates 128 macrocells, 8 dedicated input pins, and a programmable AND/OR/XOR logic fabric with a typical propagation delay of 35 ns through the logic array, delivering deterministic combinational and registered logic for glue-logic replacement and bus-interface consolidation. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that sits hierarchically below FPGAs and above discrete SSI/MSI glue logic in the digital design stack. CPLDs use EPROM or EEPROM (or flash) configuration memory, so they retain their logic on power-up without external boot devices, and they typically provide predictable timing with pin-to-pin delays in the 5-15 ns range, making them ideal for address decoding, bus arbitration, and state-machine implementation. The MAX 5000 series was Altera's second-generation high-density family, predecessor to the MAX 7000/MAX 3000A series. Key features of the EPM5128JC include 100% factory-tested logic, 128 macrocells with programmable I/O architecture, a global clock network, and an in-system-erasable EPROM cell that allows unlimited reconfiguration under UV erasure for ceramic-windowed packages. The device operates from a single 5 V supply, supports both combinatorial and registered logic per macrocell, and provides JTAG-compatible boundary-scan testability per IEEE 1149.1. The architectural foundation is a programmable AND/OR array: each macrocell contains a sum-of-products logic block, a programmable flip-flop, and an output enable / polarity control. The interconnect fabric uses Altera's classic Universal FastTrack (in MAX 5000) routing, which guarantees fixed and predictable timing for every signal path regardless of logic placement, an important consideration when migrating from discrete PAL/GAL devices. Typical applications include legacy 5 V bus-interface bridging (ISA, VME, STD), state-machine controllers in industrial PLCs, peripheral glue-logic consolidation in printers and disk controllers, address decoding for 8-bit and 16-bit microprocessor systems, and pin-compatible replacements for multiple TTL/MSI packages. The ceramic PLCC-68 (JC) package is well-suited for prototypes and high-reliability applications where plastic packages are unsuitable. Designers should note that the MAX 5000 family is an obsolete legacy family; current designs should target MAX 3000A, MAX II, or MAX V CPLDs in equivalent logic densities, or use small low-cost FPGAs (Cyclone IV / MAX 10) when supply assurance matters. The ceramic JLCC windowed package is preferred for engineering development because UV erasure allows iterative reprogramming; production plastic-encapsulated variants should be sourced for volume runs. This page synthesizes distributor availability, drop-in cross-family alternatives, and practical design notes not consolidated in the original Altera datasheet, enabling engineers evaluating legacy MAX 5000 designs to identify drop-in replacements and migration paths.
EPM5128JC-1 - 128-Macrocell MAX 5000 CPLD 40ns | Altera
The Altera EPM5128JC-1 is a high-density UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 macrocells and 2,500 usable gates in a 68-pin ceramic windowed CQCCJ (J-Lead) package. Per the Altera MAX 5000 datasheet, the device operates from a single 5 V supply (4.75 V to 5.25 V) and supports pin-to-pin propagation delays of 40 ns at the commercial speed grade -1, with a maximum toggle frequency of 62.5 MHz. The non-volatile, erasable architecture makes it suitable for prototyping and field-programmable production runs where in-system re-programmability is desired. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that uses a sum-of-products (AND/OR) architecture with on-chip EEPROM or EPROM cells to retain the configuration permanently without external boot memory. CPLDs sit between simple SPLDs/GALs and larger FPGAs in the programmable logic hierarchy, offering deterministic timing, very low power consumption, and instant-on behavior at boot. The MAX 5000 family was Altera's third-generation CPLD, superseded by MAX 7000 and later MAX II families, but remains in use in legacy industrial, telecom, and aerospace systems. Key features of the EPM5128JC-1 include 128 macrocells organized in Logic Array Blocks (LABs), programmable interconnect with predictable timing, a JTAG-compatible programming interface, and 100% AC testability at production. The ceramic windowed J-lead package (CQCCJ-68) allows the EPROM-based configuration to be erased with UV light, supporting iterative prototyping and program updates that flash-based CPLDs cannot match. Architecturally, the device combines multiple PAL-like macrocells with a global programmable interconnect array (PIA), giving designers 5 ns internal register-to-register delay budgets that are independent of routing path length. This deterministic timing model simplifies static timing closure versus FPGA fabrics. Typical applications include legacy industrial glue logic, address decoding and bus interfacing for microprocessors/microcontrollers, state-machine controllers in telecom infrastructure, prototyping of TTL/74-series replacement logic, and aerospace/military systems that require UV-erasable, non-volatile programmable logic with long-term traceability. Today the part is mainly sourced through distributors stocking end-of-life inventory. When designing with this part, prefer the latest revision tool flow (MAX+PLUS II or Quartus II legacy support) and budget for ceramic package clearance. UV erasure requires the quartz window to remain uncovered during reprogramming cycles. This page synthesizes distributor pricing, parametric comparison with same-family MAX devices, and lifecycle guidance not consolidated in the original datasheet.
EPM5128JC-2 - 128-Macrocell UV PLD, 45ns, CQCC-68 | Altera
The Altera EPM5128JC-2 is a high-density, UV-erasable programmable logic device (PLD) from the classic MAX 5000 family, offering 128 macrocells, 7 dedicated inputs, and a maximum propagation delay of 45 ns in a 68-terminal ceramic quad flat pack (CQCC) windowed package. It operates at a maximum clock frequency of 50 MHz and is implemented in CMOS technology optimized for high-speed, high-density glue-logic applications. The J-suffix package with C-windowed top is intended for engineering development and field re-programmability via ultraviolet erasure. A PLD (Programmable Logic Device) is a generic class of digital semiconductor that allows the designer to implement custom combinatorial and sequential logic by programming an on-chip AND/OR array, in this case a sum-of-products macrocell fabric. Within the broader programmable logic hierarchy, the EPM5128 sits at the entry-level/mid-density tier between classic PAL/GAL devices and modern SRAM-based FPGAs, and is part of the one-time-programmable (OTP) or UV-erasable segment that was eventually superseded by EEPROM/Flash-based MAX 7000/MAX 3000 and SRAM-based FLEX/ACEX families. Key features of the EPM5128JC-2 include 128 macrocells of sum-of-products logic, a 45 ns pin-to-pin propagation delay, 50 MHz maximum internal counter frequency, 7 dedicated data inputs, and 7.5 ns input setup time. The device also provides 12 mA DC output drive on each I/O pin, support for both combinatorial and registered macrocell configurations, and an internal global clock network. The J-suffix windowed ceramic package allows up to 1000 erase/program cycles for iterative development and field firmware changes. From an architecture perspective, the EPM5128JC-2 uses a programmable AND array feeding a fixed OR array within each macrocell, with output polarity and feedback paths that are user-configurable. The 50 MHz fCNT figure is derived from the internal counter path rather than the slower tPD path, so designers should follow the 45 ns tPD specification for combinational paths and the 50 MHz figure for registered/counter paths. The 7 dedicated inputs are useful for synchronous control signals such as clock, clock enable, asynchronous clear, and output enable that need to be routed to every macrocell. Typical applications for the EPM5128JC-2 include bus-interface glue logic in 5 V VME and Multibus II systems, state-machine controllers in industrial automation, address decoding for legacy 8-bit and 16-bit microprocessors such as the 8086, 68k, and 68000, peripheral chip-select generation, and DMA/arbitration logic. The wide 5 V tolerance, 128 macrocell density, and 45 ns tPD made it a workhorse for board-level designers in the late 1980s and early 1990s, and windowed ceramic parts remain in service today in long-lifecycle military and aerospace programs where PCB redesign is impractical. A key design consideration is that the J-windowed ceramic package is larger and more expensive than plastic PLCC alternatives, so production builds should migrate to the LC (PLCC-68) or GM (PGA-68) variants once the design is stable. Designers should also budget for the 7 dedicated input pins being non-allocatable as I/O, which reduces effective I/O count compared to the raw macrocell figure. This page synthesizes distributor pricing, package-level drop-in alternatives from the MAX 5000 family, and practical design notes for legacy PLD migration that are not present in the original Altera datasheet.
EPM5128JI - 128-Macrocell MAX 5000 UV PLD | Intel / Altera
The Intel / Altera EPM5128JI is a 128-macrocell high-speed, high-density UV-erasable programmable logic device (PLD) from the classic MAX 5000 family. The part provides 128 macrocells of combinational and registered logic in a 68-terminal ceramic CQCC windowed (J-lead) package and operates with a typical propagation delay of 55 ns and a maximum clock frequency of 40 MHz on a CMOS process. The "J" suffix denotes the ceramic J-leaded CQCC carrier and the "I" indicates the industrial operating temperature grade. A UV-programmable Logic Device (PLD) is an early-generation programmable logic IC that uses floating-gate CMOS memory cells to store the user's logic. UV PLDs like the EPM5128JI are erased by exposing the die through a quartz window to ultraviolet light, then reprogrammed - which is why EPM5128JI is shipped in a ceramic windowed package. UV PLDs sit in the hierarchy: PLD -> programmable logic -> digital logic IC -> semiconductor. They preceded modern SRAM-based CPLDs and FPGAs and are still found in long-lifecycle industrial and military programs. Key features include 128 macrocells, 55 ns pin-to-pin propagation delay (tPD), 40 MHz maximum internal operating frequency, CMOS technology with low standby current, JTAG-less in-system configuration support via the Altera MAX+plus II programming flow, and a 68-terminal ceramic CQCC (J-lead, windowed) package. The windowed ceramic carrier allows repeated erasure and reprogramming, which is why this package form factor remains common in legacy test, military, and avionics designs where code revisions are expected over a 20-30 year program lifetime. The EPM5128JI uses Altera's classic MAX architecture: a global interconnect array feeding an AND/OR logic fabric followed by a configurable output macrocell with a programmable flip-flop. Because the device is pin-compatible with later MAX 5000 speed grades (-2, -1) and compatible with Altera's industry-standard MAX+plus II development flow, it remains a known quantity in maintenance and retrofit programs. Typical applications include industrial control logic, legacy glue logic in military and avionics systems, custom state machines, address decoding, and bus-interface bridging. The wide operating temperature range and ceramic package make the EPM5128JI suitable for harsh-environment programs. When designing with this device, note that 55 ns tPD is too slow for any high-speed synchronous interface - it is best used for control-plane logic, address decoding, and slow asynchronous glue. Programming requires a UV eraser and an Altera-compatible programmer, so for new designs consider the EPM5128JC (plastic PLCC) or a modern MAX II/MAX V CPLD instead. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 5000 family, and practical design notes that are not found in the original manufacturer datasheet.
EPM5128JI-2 - 128-Macrocell UV PLD, 45ns, MAX 5000 | Altera
The Altera EPM5128JI-2 is a UV-erasable programmable logic device (PLD) from the classic MAX 5000 family, providing 128 macrocells, 7 dedicated inputs, 52 user I/O pins, and a 45 ns propagation delay in a ceramic J-leaded (JI) through-hole package. The part operates from a single 4.5 V to 5.5 V supply, supports a maximum clock frequency of 50 MHz, and is characterized across the industrial -40 C to +85 C temperature range, making it suitable for legacy industrial, telecom, and military systems still in long-term production or sustainment programs. A PLD (Programmable Logic Device) is a class of digital integrated circuit whose logic function is defined after manufacturing by the end user. PLDs sit in the broader hierarchy of digital logic devices: PLD -> CPLD (Complex PLD) -> programmable logic -> semiconductor. The MAX 5000 series uses a CMOS EPROM cell with UV-erasable window (JI suffix) and represents Altera's second-generation high-density PLD architecture, predating the modern MAX 7000/3000A families that later moved to in-system programmability (ISP) and lower-cost plastic packages. Key features include 128 macrocells of combinational and registered logic, 52 bidirectional I/O pins organized into architecturally flexible logic array blocks (LABs), and a worst-case pin-to-pin propagation delay (tPD) of 45 ns. The device is built on an EPROM-based CMOS process, is one-time field-programmable through a standard PLD programmer, and is erased by exposure to UV light through the ceramic package window. The JI package is a ceramic J-lead through-hole form factor with an integrated quartz erasure window, optimized for engineering development and long-term aerospace/defense programs requiring field-reprogrammability. From an architectural standpoint, the MAX 5000 family introduced Altera's segmented interconnect and LAB-based macrocell structure that became the blueprint for later MAX 7000 designs. Each macrocell contains a programmable AND/OR array, a flip-flop, and an I/O control block, with product-term allocation across LABs to optimize wide logic functions. The JI-2 speed grade represents the slower (lower-cost) industrial-speed bin, while 'JI' indicates the ceramic J-lead industrial-temperature package - all three designators together define the full ordering part number. Typical applications include legacy glue logic replacement in industrial controllers, telecom interface adapters, prototype and breadboard designs where the UV window enables rapid design iteration, and aerospace/defense sustainment programs where MAX 5000 parts remain on qualified parts lists. The 52 I/O pins are well matched to bus-interface, address-decoding, and state-machine consolidation tasks. When designing with this part, note that EPM5128JI-2 is a mature, NRND/EOL-era device - new designs should consider MAX 7000AE or MAX II/MAX V CPLDs as modern equivalents. Programming requires a legacy PLD programmer (e.g., Altera PL-ASAP or BP-1200) and the MAX+PLUS II software toolchain, both of which are end-of-life. The ceramic JI package is not drop-in compatible with plastic J-lead (JC) or PLCC packages - PCB footprint and pinout orientation differ. This page synthesizes distributor availability, same-family MAX 5000 drop-in alternatives, and design-sustainment notes not consolidated on any single datasheet or distributor listing.
EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
The Altera EPM5128LC-1 is a 128-macrocell, UV-erasable/OTP CMOS Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, housed in a 68-terminal J-lead ceramic chip carrier (windowed/erasable package) and rated for commercial 5V operation. Built on a 5 µm double-metal EPROM process, the device combines high logic density with predictable, deterministic 30 ns pin-to-pin delay, enabling straightforward replacement of discrete SSI/MSI glue logic. It provides 7 dedicated inputs and 52 bidirectional I/O pins for up to 60 inputs and 52 outputs, with 128 macrocells distributed across the MAX classic Logic Array Block (LAB) fabric. A Complex Programmable Logic Device (CPLD) is a non-volatile, electrically programmable logic IC that integrates multiple PAL/GAL-like macrocell arrays onto a single die with a global interconnect matrix. Within the broader hierarchy, the EPM5128LC-1 sits as: CPLD -> programmable logic device -> logic IC -> semiconductor IC. CPLDs are favored over discrete TTL/CMOS glue logic because they offer deterministic timing, lower board area, lower power, and field re-programmability, while remaining far simpler to use than FPGA & CPLD-class SRAM-based FPGAs. Key features include 128 macrocells, 52 user I/O pins, 7 dedicated input pins, an internal tpd of 30 ns, and an industry-standard 4-pin JTAG (IEEE 1149.1) interface for in-system boundary-scan testing and ISP. The device is offered in the LC package suffix - a windowed ceramic J-lead PLCC that supports UV erasure and re-programming, which makes the LC variant especially valuable for prototyping, design iteration, and low-volume engineering builds. Typical applications include address decoding for 8/16-bit microprocessor and microcontroller systems, bus-interface glue logic between legacy peripherals, board-level control sequencers, and retrocomputing or industrial controller logic. The wide 5V operating range and CMOS input thresholds make the EPM5128LC-1 compatible with TTL and CMOS logic families used in 1980s-1990s designs. When designing with this device, verify JTAG chain order against other boundary-scan devices and note that Altera legacy MAX 5000 software support requires MAX+PLUS II or Quartus in legacy compatibility mode.
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
The Altera EPM5128LC2 is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It operates from a single 5 V supply and offers a pin-to-pin propagation delay of 45 ns, making it suitable for replacing multiple TTL/74-series glue-logic packages with a single in-system programmable device. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines the integration density of an FPGA with the deterministic timing and instant-on behavior of classic PAL/GAL architectures. Within the broader semiconductor hierarchy, CPLDs sit alongside FPGAs under the programmable-logic umbrella, but unlike SRAM-based FPGAs they retain their configuration in on-chip EPROM/EEPROM cells and require no external boot memory. The MAX 5000 series specifically targets TTL-compatible, 5 V-only glue-logic consolidation and bus-interface replacement in industrial control, telecommunications, and legacy computer designs. Key features of the EPM5128LC2 include 128 macrocells, 8 LABs linked by a global PIA, 1 dedicated global clock input plus shared input/clock pins, JTAG/IEEE 1149.1 boundary-scan support, and an extended operating temperature grade. The device is offered in a Pin-Grid-Array (PGA) ceramic package suitable for socketed or through-hole industrial assemblies, with the 'LC2' suffix indicating the lower-power CMOS process and the commercial speed/power grade. Architecturally, the MAX 5000 device uses an EPROM-based configuration cell so the programmed logic is retained without power, enabling true instant-on behavior at power-up - a defining advantage over SRAM FPGAs in deterministic boot applications. Each macrocell contains a programmable AND/OR array with a flip-flop, and the deterministic PIA routing provides predictable, fixed propagation delays that simplify static timing closure in control and interface designs. Typical applications include TTL/74-series glue-logic consolidation in industrial controllers, address decoding and bus interfacing in legacy x86 and embedded CPU designs, state-machine and sequencer replacement in telecommunications line cards, and I/O expansion for microprocessor-based systems. The 5 V supply, ceramic packaging, and -40 C to +85 C extended commercial operating range also suit it to harsh-environment industrial equipment. When designing with the EPM5128LC2, engineers should note that the MAX 5000 family has been classified as mature/EOL by Altera (now part of Intel), so long-term production planning and last-time-buy windows must be confirmed with the manufacturer before committing to new designs. Use the Altera MAX+PLUS II or Altera Quartus legacy support tools for design entry, fitting, and programming of this older device. This page synthesizes distributor pricing, same-brand drop-in alternatives from the MAX 5000 family, and practical design notes that go beyond what the manufacturer datasheet alone provides.
EPM5130GI - 128-Macrocell MAX 5000 UV PLD | Altera
The Altera EPM5130GI is a UV-erasable, high-density CMOS Programmable Logic Device (PLD) from the classic MAX 5000 family, delivering 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It supports one global external clock, provides 19 dedicated inputs, 68 total inputs, and 48 bidirectional I/O lines, with a propagation delay (tPD) of 55 ns and a maximum clock frequency of 33.3 MHz, all housed in a ceramic Pin Grid Array (PGA) windowed package suitable for prototype and low-volume engineering work. What is a Programmable Logic Device (PLD)? A PLD is a general-purpose digital integrated circuit whose internal logic function is defined by the end user rather than the device vendor. PLDs sit in the broader taxonomy of logic semiconductors, beneath programmable logic and above fixed-function gate arrays, and historically bridge the gap between discrete 7400-series SSI/MSI TTL packages and modern FPGAs. The MAX 5000 family is a second-generation multi-level AND-OR architecture that consolidated dozens of SSI/MSI functions into one programmable part, an early step toward the high-density CPLDs and FPGAs that dominate today's logic design landscape. Key features of the EPM5130GI include a 100% generic, JTAG-free architecture with 100% interconnect coverage between LABs and macrocells, individual macrocell register control, programmable output polarity, and a 5 V CMOS core compatible with TTL input levels. Programmable output slew-rate control, 100% testable with a high fault coverage, and a ceramic-windowed PGA package suitable for erasure by ultraviolet light round out the silicon feature set. The MAX 5000 architecture separates logic from I/O using a Programmable Interconnect Array (PIA) that is fixed in delay regardless of routing, simplifying timing analysis. Each macrocell contains a programmable AND/OR/Register structure with a D flip-flop and a tri-state output buffer, allowing every output to be configured as combinatorial or registered. The PIA delays are predictable, which historically allowed the MAX 5000 family to replace large amounts of SSI/MSI logic with a single, fully deterministic device. Typical applications for the EPM5130GI include legacy industrial control glue logic, bus-interface address decoding, state-machine implementation, and replacement of large SSI/MSI TTL boards. The 55 ns tPD makes the device suitable for microprocessorial peripheral decoding, peripheral-interface state machines, and older control systems where the surrounding logic is still 5 V TTL. When designing with this part, note that the 'GI' suffix denotes a ceramic PGA windowed (UV-erasable) package intended for prototype and engineering use; production users normally move to the plastic-windowless or one-time-programmable variants after design freeze. Power sequencing should respect standard 5 V CMOS rails, and unused I/O pins must be left floating per MAX 5000 family guidelines. This page synthesizes distributor pricing, drop-in alternatives, and engineering notes not found in the original Altera datasheet alone, so that designers maintaining legacy systems can quickly evaluate the EPM5130GI against modern and same-family substitutes.
EPM5130GM883B - Military CPLD, MAX 5000, 100-pin CPGA | Altera
The Altera EPM5130GM883B is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, screened to MIL-STD-883B specifications and housed in a 100-terminal Ceramic Pin Grid Array (CPGA) package designated S-CPGA-P100. The /883B suffix indicates Class B MIL-STD-883 screening, which qualifies the device for aerospace, defense, and other high-reliability programs requiring extended temperature operation and traceability. The MAX 5000 architecture combines multiple Logic Array Blocks (LABs) and a programmable interconnect array, providing non-volatile, instant-on logic with deterministic timing suitable for replacing multiple SSI/MSI glue-logic devices. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PLDs and FPGAs in the programmable logic hierarchy. CPLDs use EEPROM or flash-based configuration cells and a continuous, predictable routing fabric with predictable pin-to-pin delays. Compared to discrete 74-series logic, a CPLD reduces board area, simplifies BOM, and adds design flexibility, while offering faster, more deterministic timing than an FPGA. The EPM5130GM883B is one of the highest-density members of the legacy MAX 5000 family, with up to 5,000 usable gates, making it appropriate for state machines, address decoding, bus arbitration, and peripheral control in legacy military systems. Key features include up to 5,000 usable gates, 128 macrocells, up to 60 user I/O pins, propagation delays on the order of 15 ns, and a 5 V tolerant core designed for TTL-compatible logic levels. The non-volatile EEPROM configuration means the device powers up fully operational without external boot memory, which is critical for safety-critical systems where determinism at power-on is mandatory. Programmable security bits protect the user's design against reverse engineering. The EPM5130GM883B utilizes Altera's MAX architecture with multiple Logic Array Blocks (LABs), each containing 16 macrocells. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable I/O architecture. The hierarchical interconnect network (PIA) provides predictable routing delays regardless of fan-out, which is a defining advantage over FPGA-based solutions. Typical applications include military avionics, aerospace flight-control subsystems, missile guidance electronics, radar signal processing front-ends, and legacy defense retrofit programs where long-term product lifecycle and MIL-STD-883B traceability are required. The 5 V tolerance and instant-on behavior suit it for retrofits into older 5 V digital designs. A key design consideration when using this part is that the MAX 5000 family is mature/legacy. Engineers should validate long-term availability, second-source the design where possible, and consider newer MAX II/MAX V CPLDs in 3.3 V designs unless MIL-STD-883 screening is mandatory. This page synthesizes distributor pricing, MIL-STD-883B screening details, application context, and design notes that are not aggregated in a single datasheet source. Information reflects the Altera MAX 5000 datasheet family and distributor inventory snapshots as of 2026-09-12.
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
The Altera (now Intel) EPM5130JC-1 is a high-density UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 2,500 usable gates organized as 128 macrocells in 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), housed in an 84-pin PLCC package. The device operates from a single 5 V supply with 128 macrocells, supports a maximum clock frequency of 62.5 MHz, and delivers a pin-to-pin propagation delay of 40 ns at commercial-grade timing. A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-backed programmable logic IC that combines the integration density of an FPGA with the deterministic timing, instant-on behavior, and simple programming model of a classic PLD. Within the broader programmable-logic taxonomy, the MAX 5000 sits between classic 7400-series SSI/MSI glue logic and modern SRAM-based FPGAs; it functions as a glue-logic replacement, bus-interface bridge, or state-machine engine in industrial, telecom, and military systems where deterministic 5 ns-class pin-to-pin delays and zero-config startup are mandatory. Key features include 19 dedicated inputs, a shared input/clock architecture, 80 I/O pins in the 84-pin PLCC package, and one global clock pin with user-configurable polarity. The architecture uses 100% CMOS EEPROM cells (for MAX 5000AE variants) or EPROM (for the EPM5130 JC-1, which is UV-erasable through a quartz window). Logic is implemented using sum-of-products expressions evaluated by the AND-OR array, with each macrocell containing a programmable flip-flop, select-mux, and feedback path. Typical applications include industrial-control state machines, bus-interface glue logic (8086/68000 glue), address decoding, DRAM controller glue, and legacy 7400-series logic consolidation. The device's 5 V tolerance and deterministic timing also make it suitable for replacing multiple discrete TTL/CMOS packages in designs where PCB real estate is at a premium. This page synthesizes distributor stock, drop-in same-package alternatives from the MAX 5000 family, and design notes that complement the manufacturer datasheet.
EPM5130JI - 128-Macrocell MAX 5000 EPLD, 33.3 MHz | Altera
The Altera EPM5130JI is a CMOS UV-erasable programmable logic device (EPLD) from the MAX 5000 family, featuring 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected through a Programmable Interconnect Array (PIA), and housed in a ceramic-windowed J-lead package for in-system erasure with ultraviolet light. An EPLD (Erasable Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that predates modern flash-based CPLDs and FPGAs. The MAX 5000 family sits in the historical Altera (now Intel) product lineage as a high-density, high-speed CMOS EPLD family built around a sum-of-products macrocell architecture with a unified interconnect matrix. This places the EPM5130JI in the hierarchy: macrocell -> LAB -> EPLD -> programmable logic device -> digital IC -> semiconductor. Key features include a maximum clock frequency of 33.3 MHz, a propagation delay of 55 ns (tPD), 1 dedicated external clock input with shared input/clock pin capability, and a 100% factory-tested logic macrocell count of 128. The device is built on a 0.75-micron CMOS EPROM process and is packaged in a ceramic J-leaded chip carrier (JLCC) with a quartz erasure window - a hallmark of the MAX 5000 family. The EPM5130 architecture uses a Programmable Interconnect Array to route signals between LABs, providing fast, predictable timing for state-machine and glue-logic designs. The 128 macrocells each contain a programmable AND/OR array and a configurable flip-flop, supporting registered, combinatorial, and buried logic. Power consumption is roughly 250 mW at typical CMOS supply levels, and inputs are TTL-compatible. Typical applications include legacy telecom interface glue logic, industrial control state machines, prototyping platforms for ASIC replacement, and educational laboratory courses on programmable logic. The UV window allows engineers to erase and re-program the device dozens of times, making it attractive for design iteration. When designing with the EPM5130JI, note that the ceramic JLCC package requires a through-hole socket or careful hand-soldering and that UV erasure takes 20-30 minutes of exposure to 12,000 uW/cm² UV light. The device operates from a single 5V supply and is a commercial-temperature-grade part. This page synthesizes legacy distributor stock data, J-lead package information, and cross-family replacement guidance not consolidated in the original Altera datasheet, helping engineers evaluate the part for both new designs and legacy repair scenarios.
EPM5130LC - 128-Macrocell MAX 5000 UV-Erasable CPLD | Altera
The Altera EPM5130LC is a 128-macrocell, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from Altera's MAX 5000 family, fabricated in CMOS technology and housed in a J-Lead Ceramic Chip Carrier (JLCC) package. It delivers a pin-to-pin propagation delay of 55 ns, supports a maximum internal clock frequency of 50 MHz, and provides 8 Logic Array Blocks interconnected by a Programmable Interconnect Array (PIA). The device integrates 19 dedicated inputs and 48 bidirectional I/O lines, totaling 68 inputs, and is supplied across a 4.5 V to 5.5 V VCC range with TTL-compatible I/O. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that uses EPROM, EEPROM, or flash memory cells to store configuration. The MAX 5000 family predates the MAX 7000/3000 series and belongs to Altera's classic UV-erasable/OTP taxonomy, sitting at the base of the programmable logic hierarchy: CPLD -> PLD (Programmable Logic Device) -> programmable logic IC -> semiconductor. These parts retain their configuration when powered off and are widely used in glue-logic and bus-interface designs. Key features include 128 macrocells, 48 user I/O, 8 LABs, 1 global clock input, 68 total inputs (dedicated + I/O), and a 55 ns tPD. The chip is built on a 0.7 um CMOS EPROM process and supports in-system programming via Altera's A+PLUS or MAX+PLUS II toolchains. Typical applications include bus-interface and address decoding for legacy microprocessors, glue-logic replacement for 74LS/74F TTL gates, asynchronous state-machine controllers, and industrial control boards where UV-erasable parts are preferred for security reasons. Compared to SRAM-based FPGAs, the EPM5130LC is non-volatile and boots in microseconds. When designing with this device, ensure the VCC rail stays within 4.5 V to 5.5 V and account for the 55 ns propagation delay in worst-case timing analysis. Provide proper decoupling on VCC/GND pairs and respect the 48-I/O and 68-input budgets when allocating pins. This page synthesizes distributor pricing, drop-in MAX-family alternatives, and practical design notes not found in the original Altera datasheet, providing engineering value beyond raw parameter repetition.
EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera
The Altera (Intel) EPM5130QC-1 is a UV-Erasable / OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, supplied in a 100-pin PQFP package with a 0.635 mm terminal pitch. Built on a CMOS process, the device integrates 5130 equivalent logic cells (macrocell class) intended for high-density glue-logic and state-machine replacement in digital systems. The "-1" speed grade and "QC" package code indicate a commercial-temperature grade PLD housed in a windowed ceramic PQFP suitable for prototype development and UV erasure reprogramming. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on semiconductor that combines multiple PAL/GAL-style AND/OR arrays on a single die with on-chip programmable interconnect, EEPROM or EPROM storage, and a fixed number of macrocells. In the broader taxonomy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers predictable timing, deterministic propagation delay, and pin-locking capability while providing significantly higher logic density than discrete 22V10/26V12-era PLDs. CPLDs are typically used as address decoders, bus interface bridges, peripheral glue, and state machines that need to boot in microseconds without external configuration memory. Key feature highlights of the EPM5130QC-1 include its 5130 usable gates (marketing name), 128 macrocells, EPROM-based UV-erasable non-volatile configuration, and a -1 speed grade aimed at general-purpose commercial logic integration. The device operates from a single 5 V supply, supports JTAG-style boundary-scan testing (per MAX 5000 family features), and offers output macrocells with programmable polarity, register/ combinatorial modes, and tri-state control. Compared with later MAX 7000/MAX II families, the MAX 5000 retains the older EPROM cell, requiring a quartz window package for erasure. Architecturally, the MAX 5000 family uses an EPROM-based AND array feeding a fixed OR array per macrocell, with each macrocell containing a flip-flop, output enable, and programmable polarity bit. Programming is performed via industry-standard device programmers and a JTAG/byte-blaster-like interface; erasure of windowed parts (QC package, ceramic) requires 20-30 minutes of 254 nm UV exposure. The 100-pin PQFP provides ample I/O for bus-oriented glue-logic tasks, and the 0.635 mm pitch is compatible with conventional surface-mount assembly and hand-soldered rework. Typical applications for the EPM5130QC-1 include industrial control boards, telecommunications equipment glue logic, address decoding for microprocessor/microcontroller systems, peripheral bus bridges (ISA-to-local bus, parallel-port expansion), and educational/prototype lab platforms that require an erasable, reprogrammable logic device. New designs are usually served by MAX II or MAX V devices, but the EPM5130QC-1 remains in service as a form-fit-function replacement for legacy boards where re-layout is impractical. When designing with the EPM5130QC-1, observe the I/O and supply sequencing rules documented in the MAX 5000 datasheet, and ensure all unused I/O pins are configured as outputs with the output-enable disabled or tied to defined logic levels. Because the part is UV-erasable only, a socket is recommended during firmware bring-up. For high-volume production where UV erasure is undesirable, consider migrating to a one-time-programmable (OTP) MAX 5000 variant or to a MAX 7000S / MAX II successor. This page synthesizes distributor pricing, drop-in same-package alternatives sourced from the Altera MAX 5000 family, datasheet availability, and design considerations that are not compiled in the original manufacturer datasheet PDF.
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
The Intel (Altera) EPM5130WC-1 is a 128-macrocell ultraviolet-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in a 100-pin ceramic windowed QFP (Ceramic Quad Flat Pack) package. It delivers a pin-to-pin propagation delay of 40 ns, a maximum clock frequency of 50 MHz, and a logic density suitable for glue-logic, state-machine, and bus-interface consolidation. The ceramic windowed package allows the device to be erased with UV light and reprogrammed, making it appropriate for prototyping and engineering development. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a central interconnect matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs and below FPGAs; they offer predictable timing, deterministic pin-to-pin delays, and instant-on configuration from on-chip EEPROM/EPROM, which makes them especially valuable in address decoding, peripheral control, and bus-interface bridging where sub-nanosecond timing guarantees are required. The EPM5130WC-1 supports up to 100 user I/O through the QFP package, integrates 128 macrocells across multiple Logic Array Blocks (LABs), and provides a programmable interconnect array that maintains consistent timing regardless of how a design is placed. Its UV-erasable windowed package allows iterative reprogramming during development cycles. The MAX 5000 architecture is fabricated on a CMOS EPROM process, providing non-volatile configuration storage. Architecturally, the MAX 5000 family uses a programmable AND/OR array feeding a configurable macrocell register that can be configured as combinational or registered output. Each macrocell includes a flip-flop with programmable clock, clear, and preset controls. The deterministic interconnect fabric guarantees a fixed propagation delay independent of routing density, simplifying static timing analysis. Typical applications include bus-interface glue logic, peripheral address decoding, state-machine controllers, and legacy industrial control systems that require UV-reprogrammable non-volatile logic. The ceramic QFP package is also suited to military and aerospace-grade designs with MIL-STD-883B screening variants available in the MAX 5000 family. When designing with the EPM5130WC-1, account for its 40 ns propagation delay when targeting high-speed bus interfaces and provide proper decoupling on all VCC pins. UV windowed ceramic packages require a label covering the quartz window after programming to prevent accidental erasure from ambient light exposure. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers source and qualify obsolete Altera MAX 5000 CPLDs.