FPGA & CPLD
Products (6352)
EPM9560RC208-4 - MAX 9000 CPLD 560 Macrocells | Altera
The Altera EPM9560RC208-4 is a high-density Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells in a 208-pin RQFP (Power Quad Flat Pack) package. The device is built on an EEPROM-based architecture that delivers non-volatile, in-system programmable logic with 12,000 usable gates and a 4 ns speed grade pin-to-pin logic delay. It supports in-system programmability via the IEEE 1149.1 JTAG interface and operates from a 5 V supply with commercial and industrial temperature grade options. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PLDs and FPGAs in the programmable logic hierarchy. Compared to an FPGA, a CPLD provides predictable timing, instant-on behavior from EEPROM configuration cells, and high pin-to-pin performance for glue-logic, bus interfacing, and state-machine applications. The MAX 9000 family represents Altera's highest-density EEPROM CPLD generation, designed for wide bus bridging, fast address decoding, and high-speed control logic consolidation. Key features of the EPM9560RC208-4 include 560 macrocells organized across 16 Logic Array Blocks (LABs), maximum operating frequency of 118.3 MHz, 16 dedicated input pins plus 96 I/O pins (208-pin RQFP), and a 4 ns combinatorial propagation delay (tPD). The device also provides 4 global clock inputs with programmable clock management, in-system programming via JTAG, and MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V interface levels to bridge multiple logic domains on a single board. From an architectural perspective, the MAX 9000 family integrates an enhanced interconnect network called the Programmable Interconnect Array (PIA), which routes signals between LABs with predictable, deterministic timing. Each LAB contains 16 macrocells with shared expander product terms, enabling efficient implementation of wide gating functions and arithmetic logic. The 4 ns speed grade is the slowest in the family; faster -3, -2, and -1 grades are available for timing-critical designs requiring tighter propagation delay budgets. Typical applications include PCI bus interface bridging, high-speed address decoding for microprocessors, glue-logic consolidation in telecom backplane designs, and control logic in industrial automation equipment. Designers choose the MAX 9000 family when instant-on behavior, deterministic timing, and non-volatile configuration are required without the cost or complexity of an SRAM-based FPGA. When designing with this part, ensure 5 V VCC stability and provide a clean JTAG chain to support ISP. For new designs, prefer MAX II or MAX V devices from Intel (formerly Altera); the EPM9560RC208-4 is recommended for legacy maintenance, form-fit-function replacement, or where the original MAX 9000 design files are preserved. This page synthesizes distributor availability, parametric alternatives, and legacy CPLD design considerations not found in the manufacturer datasheet alone, making it a practical reference for engineers maintaining installed-base MAX 9000 designs.
EPM9560RC208-4C - MAX 9000 CPLD 560 Macrocell | Altera
The Altera EPM9560RC208-4C is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and 208-pin RQFP (Power Quad Flat Pack) packaging, with a -4 speed grade corresponding to a 12 ns pin-to-pin propagation delay. It operates from a 5.0 V supply and is a member of the MAX 9000 EEPROM-based programmable logic family. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of an FPGA with the non-volatile, instant-on characteristics of a PAL/PLD. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic device. MAX 9000 devices use EEPROM configuration cells, so they retain their design after power-down and require no external configuration memory, unlike SRAM-based FPGAs. The EPM9560RC208-4C provides 560 macrocells organized into 12 logic array blocks (LABs), with 12,000 usable gates and 164 maximum user I/O pins. The -4 speed grade delivers 12 ns pin-to-pin logic delays and supports system clock frequencies up to 125 MHz. The 208-pin RQFP package offers a high I/O-to-package ratio for dense board-level glue logic, bus interfacing, and state machine implementations. MAX 9000 devices are built on an EEPROM process that provides in-system programmability (ISP) via the JTAG interface, allowing field upgrades without removing the device from the board. The architecture uses a programmable interconnect array (PIA) to route signals between LABs, giving deterministic timing that simplifies worst-case timing analysis compared with segmented FPGA routing. Typical applications include PCI bus bridging, DSP/processor glue logic, memory controllers, industrial control state machines, and legacy system replacement where instant-on operation and 5 V compatibility are required. The 5 V core also allows direct interfacing with TTL and 5 V CMOS logic without level shifters. When designing with the EPM9560RC208-4C, note that it is a mature/legacy device; Altera (now Intel) has issued discontinuance notices for selected MAX 9000 ordering codes, and the 208-pin CQFP package has been replaced by the form-fit-functionally equivalent 208-pin RQFP. Verify availability and consider the RQFP variant for new designs. This page synthesizes distributor availability, drop-in ordering-code alternatives, and practical design notes for the EPM9560RC208-4C that are not consolidated in the manufacturer datasheet, helping engineers evaluate replacement and sourcing options quickly.
EPM9560RC208-5 - 560-Macrocell MAX 9000 CPLD, 5ns, 5V | Altera
The Altera EPM9560RC208-5 is a 560-macrocell, 12,000-gate Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on a 5V CMOS EEPROM process and housed in a 208-pin RQFP (Plastic Quad Flat Pack) package. Speed grade "-5" corresponds to a 5 ns pin-to-pin propagation delay (tPD) and approximately 117.6 MHz internal fCNT, making it one of the fastest members of the MAX 9000 family. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that combines the integration density of an FPGA with the deterministic timing and predictable routing of a classic PAL/GAL architecture. The MAX 9000 family hierarchy is: CPLD -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Each MAX 9000 device provides multiple Logic Array Blocks (LABs), a global interconnect called the Programmable Interconnect Array (PIA), and I/O control blocks that support 3.3V/5V mixed-voltage operation. Key features of the EPM9560RC208-5 include 560 macrocells, 16 Logic Array Blocks, 16 dedicated inputs, 149 user I/O pins, 772 flip-flops, and 12,000 usable gates. The device supports in-system programmability through the JTAG-compliant IEEE Std 1149.1 boundary-scan interface, plus 5V in-system programming via the dedicated programming pins. The architecture delivers deterministic 5 ns tPD across all paths regardless of logic utilization - a key advantage over SRAM-based FPGAs for timing-critical glue logic. Typical applications include high-speed bus-interface glue logic, FIFO control, state-machine replacement for ASICs, address decoding in multiprocessor designs, and PCI/bus arbitration circuits. The 208-pin RQFP footprint provides 149 usable I/O lines, which is enough headroom for 32-bit databus plus extensive control signalling without external bus transceivers. When designing with this device, ensure the 5V supply is well-decoupled with 0.1 uF ceramics placed within 5 mm of each VCC pin pair, and respect the 5.0V absolute-maximum supply rail - the device is not 3.3V-tolerant on its inputs without proper level shifting. JTAG programming requires TCK, TMS, TDI, TDO tied to the board test header; pull-ups of 10 kohm on TMS and TDI are recommended per the MAX 9000 family datasheet. This page synthesizes verified distributor pricing, drop-in alternatives from the same EPM9560 family, and practical MAX 9000 design notes not consolidated in any single source.
EPM9560RC208-7 - MAX 9000 CPLD, 560 Logic Elements, RQFP-208 | Altera
The Altera EPM9560RC208-7 is a high-density CMOS Erasable Programmable Logic Device (EPLD) from the MAX 9000 family, delivering 560 usable gates and 16 macrocells in a 208-pin Power Quad Flat Pack (RQFP) package. It operates at a 7 ns pin-to-pin logic delay and supports in-system programmability via the IEEE 1149.1 JTAG interface plus the legacy Altera ISP port. The device is built on a 0.65 um CMOS EEPROM process with non-volatile configuration memory, so the bitstream is retained without external boot PROM. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the deterministic timing, instant-on behavior, and high-drive I/O of classic PAL/PLA architecture with much higher gate density and flexible macrocell structures. CPLDs sit in the hierarchy between simple PLDs and FPGAs: they offer predictable interconnect delays (typically <1 ns per logic block) and boot instantly from on-chip memory, making them ideal for glue logic, bus decoding, and control-plane state machines rather than data-plane DSP or pipelined datapath logic. Key features of the EPM9560RC208-7 include 208 user I/O pins, 16 macrocells arranged in four Logic Array Blocks (LABs), 5 ns tPD combinational delay, and a maximum toggle frequency above 125 MHz. The RQFP-208 package gives designers a robust surface-mount footprint with a thermal resistance suitable for industrial temperature operation, and Altera's MAX+PLUS II development environment supports schematic, VHDL, and Verilog entry. The MAX 9000 family is electrically and pin-compatible across speed grades (-7, -10, -12, -15, -20), so the same PCB can be repopulated with faster or slower parts to balance timing margin against cost. The internal architecture uses a Programmable Interconnect Array (PIA) that routes every LAB signal to every other LAB, eliminating the timing variance that plagues segmented FPGA routing fabrics. Each macrocell contains a programmable AND/OR array followed by a configurable flip-flop with D, T, JK, or SR modes, plus programmable output enable, clear, and preset controls. The 208-pin RQFP delivers 160 mA DC sink current per output, strong enough to directly drive 5V TTL buses and most 3.3V CMOS loads without external buffers. Typical applications include bus bridge decoding on legacy VME/PCI boards, address decoding for 68k and x86 microprocessor systems, glue-logic consolidation on industrial controllers, state-machine replacement on telecommunications backplane cards, and pin-compatible refresh of obsolete discrete logic on factory-automation hardware. Designers also use the EPM9560 as a 'soft glue' companion to an FPGA or microcontroller, absorbing the last few hundred gates of random logic that would otherwise force a board respin. Design consideration: when migrating from the older CQFP-208 ceramic variant, note that the RQFP-208 plastic package has a different thermal resistance and is not hermetically sealed. The Altera Product Discontinuance Notice confirms that the RQFP-208 is form, fit, and functionally equivalent to the ceramic CQFP-208 at all speed grades, so existing footprints accept either package. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)
The Intel (formerly Altera) EPM9560RC208-7N is a member of the MAX 9000 family of Erasable Programmable Logic Devices (EPLDs), built on a 0.65-micron CMOS EEPROM process and supplied in a 208-pin Power Quad Flat Pack (RQFP) surface-mount package. It is part of the long-running MAX 9000 series that targets high-density, high-pin-count glue-logic, state-machine, and bus-interface integration on a single programmable device. The "RC208" suffix indicates the RQFP-208 package, the "7" denotes a 7 ns pin-to-pin propagation delay (speed grade -7), and the trailing "N" indicates a lead-free / Pb-free process node per Altera's ordering code convention. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that retains its configuration in on-chip EEPROM, eliminating the need for an external configuration PROM. The MAX 9000 family sits in the product hierarchy between simple PLDs (PAL/GAL) and SRAM-based FPGAs, combining multi-level AND/OR array logic with macrocell-style I/O and a high pin count for bus-intensive applications. Because it is erasable and reprogrammable, designers can iterate logic without refabricating silicon, which is the core value proposition of programmable logic over fixed-function ASICs. Key features of the EPM9560RC208-7N include high logic density, 208 user I/O pins, in-system programmability through Altera's MAX+PLUS II / Quartus toolchain, and a 7 ns tPD suitable for high-speed decoder, latch, and state-machine functions. The RQFP package supports both commercial and industrial operating ranges and provides ample signal headroom for parallel bus interfaces, address decoding, and FIFO control. Architecturally, the device uses a hierarchical AND/OR plane feeding multiple Logic Array Blocks (LABs) and macrocells, with each macrocell containing a programmable flip-flop, product-term selector, and I/O control. Compared with the smaller MAX 7000 family, MAX 9000 expands usable gates and macrocell count to address wider bus interfaces and larger state machines. Typical applications include peripheral and memory address decoding in 32-bit and 64-bit microprocessor systems, glue logic and bus arbitration in industrial control boards, state-machine controllers in telecom backplane designs, and pin-compatible upgrades for older 24-pin / 84-pin PLD footprints where higher I/O and faster tPD are required. The RQFP-208 package is also favored where fine-pitch surface-mount assembly is acceptable and maximum I/O count is mandatory. When designing in this part, verify the timing model in the MAX 9000 datasheet against worst-case industrial temperature and supply voltage. Because this is an EEPROM-based legacy device, long-term availability must be confirmed with the manufacturer before new design-in; for new designs consider Altera/Intel MAX II, MAX V, or MAX 10 CPLDs as modern migration paths. This page synthesizes distributor stock observations, drop-in alternative candidates, and practical design notes that complement (not duplicate) the original MAX 9000 datasheet.
EPM9560RC208-9 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Altera
The Altera EPM9560RC208-9 is a high-density MAX 9000 family Complex Programmable Logic Device (CPLD) delivering 560 macrocells, 12,000 usable gates, and a 9 ns pin-to-pin propagation delay in a 208-pin RQFP power quad flat pack package. It belongs to the mature MAX 9000 EPLD family, originally released by Altera and now supported through Intel's legacy programmable logic portfolio after the 2015 acquisition. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks with a central interconnect matrix, offering deterministic timing, instant-on behavior, and high-drive I/O. The MAX 9000 family sits in the CPLD taxonomy as: CPLD -> EPLD -> MAX series -> MAX 9000 -> non-volatile flash/EPROM-based logic. Compared to FPGAs, CPLDs typically have lower logic density but faster, more predictable I/O-to-I/O timing and zero configuration delay, making them ideal for glue logic, bus interfacing, and control state machines. Key features of the EPM9560RC208-9 include 560 macrocells organized across 16 Logic Array Blocks (LABs), 212 user I/O pins, in-system programmability via JTAG, and a 5 V tolerant core with multi-voltage I/O support. The 9 ns tPD makes it suitable for high-speed control paths, while the 208-pin RQFP footprint provides generous I/O for bus-intensive designs. Per the Altera datasheet, all EPM9560 devices in the 208-pin RQFP are form, fit, and functionally equivalent to the older 208-pin CQFP variant that Altera has officially discontinued. Typical applications include telecommunications line cards, industrial control and instrumentation, address decoding and bus interfacing, peripheral glue logic in microprocessor systems, and legacy hardware refresh designs where the original Altera toolchain (MAX+PLUS II or Quartus) must be preserved. The wide I/O count also suits parallel data-path bridging and FIFO control logic. When designing with this part, note that the -9 speed grade provides moderate performance suited to control-plane rather than high-speed datapath use. Engineers migrating to newer Intel MAX II / MAX V CPLDs should evaluate pin-count and voltage requirements; the MAX 9000 is 5 V core and is not directly compatible with MAX V's 3.3 V core footprint. A 9 ns tPD corresponds to roughly 110 MHz internal performance, which is appropriate for most glue-logic and control applications but not for high-speed serial interfaces. This page synthesizes distributor stock data, package-equivalent speed-grade alternatives from the same EPM9560 family, and design considerations drawn from the MAX 9000 datasheet family - information not consolidated in any single manufacturer or distributor source.
EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
The Altera EPM9560RC210-20 is a high-density member of the MAX 9000 family of Complex Programmable Logic Devices (CPLDs), delivering approximately 560 macrocells (12,000 usable gates) in a 210-pin Power Quad Flat Pack (RQFP) package with -20 speed grade. The MAX 9000 family is Altera's first-generation high-density CPLD family built on a 0.65um EEPROM process, combining the non-volatility of EPROM with in-system programmability via the Altera MAX+PLUS II development environment. The -20 suffix denotes a 20ns pin-to-pin propagation delay (tPD) for combinational logic at room temperature, making it suitable for glue-logic and high-volume state-machine replacement in cost-sensitive industrial designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PAL/GAL spld devices and high-density FPGAs in the programmable logic hierarchy: PAL/GAL < CPLD < FPGA. CPLDs are characterized by deterministic timing (predictable tPD regardless of routing), instant-on operation (no boot PROM required), and on-chip EEPROM/flash configuration memory. Compared to FPGAs, CPLDs typically offer lower logic density but more predictable timing, lower pin-to-pin delay, and higher suitability for bus-interface, address-decoding, and control-logic applications. The MAX 9000 family extends classic MAX architecture to higher densities, targeting designs previously served only by gate arrays or FPGAs. Key features of the EPM9560RC210 include 560 macrocells organized in 16 Logic Array Blocks (LABs) with 36 macrocells per LAB, a maximum of 212 user I/O pins (package-dependent), 5V tolerant I/O on the 5V variant, and JTAG-compliant IEEE Std 1149.1 boundary-scan support for board-level testability. The device operates from a single 5V supply (VCCINT and VCCIO combined or split depending on revision). Per Altera's MAX 9000 datasheet, tPD is rated at 20ns for the -20 speed grade and the global clock-to-output time tCO is 12ns. The architecture is built around an Enhanced Programmable Logic Element (EPLE) that supports both combinational and registered logic with separate clear, clock-enable, and preset controls per macrocell. Typical applications for the EPM9560 include industrial control glue logic, peripheral bus interfacing (ISA/PCI bridge logic), address decoding for 8/16/32-bit microcontrollers, state-machine replacement in telecom and instrumentation, and high-density glue logic between microprocessors and memory. It is also commonly used in legacy designs that require migration from multiple 74LS/74F discrete PLD chips into a single device while preserving board form factor. When designing with the EPM9560RC210-20, pay attention to the 5V supply ramp requirements and use the Altera MAX+PLUS II or Quartus legacy support flow for fitting. The 210-pin RQFP package requires careful PCB layout - use a 0.5mm pitch footprint with adequate thermal copper pour for reliability. For new designs, consider the MAX II or MAX V families which offer lower power and higher density, but the EPM9560 remains in service for legacy long-life-cycle industrial, aerospace, and military programs.
EPM9560RC240-10 - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560RC240-10 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates and 560 macro cells with a 10 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (PowerQuad) package. It operates from a 5 V supply and supports system clock frequencies up to 144.9 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of an FPGA with the non-volatile, instant-on simplicity of a PAL. CPLDs sit between simple glue logic and full FPGAs in the programmable logic hierarchy: they offer deterministic timing, single-chip integration of bus interfaces and state machines, and no external configuration memory. The MAX 9000 family extends this concept with multiple interconnected logic array blocks (LABs) and a programmable interconnect array, delivering FPGA-like density with CPLD-like predictability. The EPM9560RC240-10 provides 560 macro cells organized into 12 LABs, each containing 16 macrocells, plus 12 dedicated input/GCLK pins and 4 dedicated input pins. Its 10 ns propagation delay (the '-10' speed grade) makes it suitable for bus-interface and control-path logic where deterministic timing matters more than raw density. The 240-pin RQFP package exposes up to 192 user I/O pins, enabling wide bus widths without external multiplexing. Architecturally, the MAX 9000 uses CMOS EEPROM technology, giving the device non-volatile configuration that is live immediately at power-up - no boot PROM or configuration controller is required. This makes it attractive for industrial control, instrumentation, and legacy telecom boards where instant-on operation and long-term availability are priorities. The 5 V core and I/O simplify interfacing to legacy TTL/CMOS peripherals without level shifters. Typical applications include PCI and ISA bus bridging, memory controllers, state-machine sequencing, address decoding, and glue logic consolidation in industrial and telecom equipment. The device is widely used as a drop-in replacement for discrete 74-series logic in existing 5 V designs. When designing with the EPM9560RC240-10, note that it is a 5 V-only device - it cannot be used in 3.3 V or lower systems without level translation. Also confirm programming support: MAX 9000 devices require a compatible device programmer and the MAX+PLUS II toolchain, which is no longer actively developed by Intel/Altera. This page synthesizes distributor availability, drop-in alternatives from the same MAX 9000 family, and practical design notes that go beyond the manufacturer datasheet, helping engineers evaluate the EPM9560RC240-10 for legacy and long-lifecycle designs.
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
The Intel (formerly Altera) EPM9560RC240-10N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates, 560 macrocells, and 16 Logic Array Blocks (LABs) in a 240-pin RQFP (Plastic Quad Flat Pack) package. According to the Altera MAX 9000 datasheet, this device operates from a 5.0 V supply, supports an internal operating frequency of 144.9 MHz, and offers a pin-to-pin propagation delay of 10 ns (the "-10" speed grade suffix), making it suitable for high-performance glue-logic, bus-interface bridging, and state-machine consolidation tasks. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die, connected through a programmable interconnect matrix (the Multiple Array MatriX, or MAX, architecture). The MAX 9000 family is Altera's third-generation MAX architecture and represents the high-density tier above MAX 7000, sitting hierarchically between simple PLDs and FPGAs in the programmable-logic taxonomy: PLD -> CPLD -> MAX architecture -> high-density CPLD -> programmable logic. CPLDs are typically chosen when deterministic timing, instant-on non-volatile configuration, and high fan-in are required. Key features of the EPM9560RC240-10N include 212 user I/O pins (the package's pin budget after subtracting dedicated supply, JTAG, and configuration pins), in-system programmability (ISP) through a standard 4-pin JTAG (IEEE 1149.1) interface, and 5.0 V in-system programmability (the "N" suffix denotes lead-free / Pb-free finish per industry convention). The device is built on a 0.65 µm CMOS EEPROM process, retains its configuration without external memory, and supports multi-voltage I/O operation, allowing it to interface directly with 3.3 V and 5.0 V logic without external level shifters. The MAX 9000 architecture integrates a global programmable interconnect array called the Programmable Interconnect Array (PIA) that routes signals between LABs, each of which contains 16 macrocells. Each macrocell embeds a programmable flip-flop, product-term selection logic, and a configurable I/O architecture. Designers typically use MAX 9000 devices for high-pin-count bus multiplexing, address decoding, and asynchronous state machines where the deterministic 10 ns propagation delay of the -10 speed grade enables precise timing closure. Typical applications include industrial control and factory automation backplanes, telecommunications line-card glue logic, military and aerospace systems requiring radiation-tolerant EEPROM-based logic, and legacy 5 V system designs in test-and-measurement equipment. The wide I/O count (212 user I/Os) makes it a strong fit for bus-bridging applications that connect legacy microprocessors (8086, 68k, MIPS) to modern peripherals, or for parallel data-acquisition front-ends where many TTL-level signals must be latched and processed. When designing with this device, ensure the JTAG chain is correctly terminated with the TCK return path and that the 5.0 V supply rail has adequate decoupling (typically 0.1 µF per supply pin plus a bulk 10 µF tantalum). Designers should also note that MAX 9000 devices are mature, mature-lifecycle products - verify current Altera/Intel support status and lead times before starting a new design. This page synthesizes current distributor stock and pricing, a curated set of drop-in and parametric alternatives from the same MAX 9000 family, and practical design notes not found in the original datasheet - providing information gain beyond what the manufacturer datasheet or single distributor listing offers.
EPM9560RC240-12 - 560 Macrocell EE PLD, 12ns PQFP-240 | Altera
The Altera EPM9560RC240-12 is a high-density Erasable-Electronic Programmable Logic Device (EE PLD) from the MAX 9000 family, featuring 560 macrocells, 772 flip-flops, and 191 user I/O lines housed in a 240-pin Plastic Quad Flat Pack (PQFP) package. The -12 speed grade corresponds to a 13.4 ns pin-to-pin propagation delay through the logic array, supporting system clock frequencies up to approximately 76 MHz in registered designs. The part operates from a 5V core supply with 3.3V or 5V tolerant I/O via configurable I/O banks, enabling mixed-voltage interfacing with legacy TTL, modern CMOS, and LVTTL peripherals on the same PCB. A Programmable Logic Device (PLD) is a non-volatile digital integrated circuit whose logic function is defined after manufacture by the end user via an EEPROM or SRAM-based configuration cell matrix. EE PLDs retain their configuration when power is removed, which distinguishes them from SRAM-based FPGAs that require a boot PROM. Within the broader taxonomy, the MAX 9000 family occupies the high-density CPLD (Complex PLD) tier - sitting between simple SPLDs/GALs and full FPGAs - and is engineered for glue-logic integration, bus interfacing, state-machine consolidation, and peripheral decoding in systems where non-volatility and deterministic timing matter more than raw gate count. Key features of the EPM9560RC240-12 include 12 ns combinatorial tPD, in-system programmability via the IEEE 1149.1 JTAG interface, 191 high-drive I/O pins organized in I/O banks with per-pin slew-rate and pull-up control, and an operating junction temperature range suitable for commercial and industrial environments. The device supports the Altera MAX+PLUS II and Quartus design flows, allowing legacy MAX-series designs to be ported without HDL rewrites. The MAX 9000 architecture combines a Logic Array Block (LAB) fabric with a programmable interconnect array (PIA), giving uniform propagation delay across all LAB-to-LAB paths. Each macrocell contains a programmable flip-flop with D, T, JK, or SR modes, plus product-term sharing logic, which makes the family efficient for wide combinatorial decoders and registered state machines rather than pipelined datapath work. Typical applications include peripheral bus decoding in PCI/ISA bridge designs, address decoding for DSP and microcontroller subsystems, register-bank expansion in telecom backplane glue logic, and industrial control PLCs where deterministic timing and non-volatile configuration are required. The wide I/O count also makes the EPM9560 useful for legacy test equipment and instrumentation front ends. Designers should note that the EPM9560RC240 series is now considered a mature / legacy device family by Altera (now Intel FPGA), with -12, -15, and -20 speed grades typically available on the distributor surplus market rather than as fully production-stocked parts. New designs should consider MAX II or MAX V CPLDs as pin-compatible modern alternatives where possible. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC240-15 - MAX 9000 CPLD 560 Macro Cells | Intel
The Intel (Altera) EPM9560RC240-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, and 191 user I/O pins, housed in a 240-pin RQFP (PowerQuad/FPQFP) package. It operates from a 5.0 V supply and delivers a 15 ns pin-to-pin propagation delay, making it a classic glue-logic and bus-interface solution for legacy 5 V systems. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the programmable logic hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, which makes it ideal for power-up sequencing, address decoding, and bus bridging. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using CMOS EEPROM technology, so the configuration is retained without an external boot device. Key features include 560 macrocells organized into logic array blocks, 12,000 usable gates, 191 user I/O pins, in-system programmability (ISP) via the JTAG interface, and a maximum internal frequency of 145 MHz. The 15 ns pin-to-pin delay provides predictable, race-free timing that is essential for combinatorial address decoding and handshake logic in microprocessor systems. The device uses 5.0 V CMOS technology with EEPROM-based configuration, giving it high noise immunity and direct compatibility with 5 V TTL/CMOS logic levels. Its 240-pin RQFP package with exposed pad supports surface mounting and provides 191 I/O for wide bus interfaces. The commercial temperature grade covers 0 C to 70 C. Typical applications include legacy microprocessor glue logic, ISA/PCI bus interface logic, industrial control backplanes, telecom line-card control, test and measurement instrumentation, and FPGA companion logic. The EPM9560RC240-15 is widely used as a drop-in replacement in existing MAX 9000 designs and for sustaining long-lifecycle industrial and defense systems. When designing with this device, note that it is a 5 V-only part and is not 3.3 V tolerant on all pins; level shifting is required when interfacing with modern low-voltage logic. Also confirm programming support, as MAX 9000 devices require a compatible JTAG programmer and the vendor's legacy programming software. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers evaluate the EPM9560RC240-15 for legacy and long-lifecycle designs.
EPM9560RC240-15C - MAX 9000 CPLD 560 Macro Cells | Intel
The Intel (Altera) EPM9560RC240-15C is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 187 user I/O pins, with a maximum internal clock frequency of 117.6 MHz and a 15 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (PowerQuad II) package. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on configuration of a PAL/PLD. CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy: PLD -> CPLD -> FPGA -> programmable logic device. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using EEPROM-based configuration cells that retain their programmed state without external configuration memory. Key features of the EPM9560RC240-15C include 560 macrocells organized into 20 logic array blocks, 12,000 usable gates, 187 configurable I/O lines, and 5.0 V in-system programmability (ISP) via the IEEE 1149.1 JTAG boundary-scan interface. The device supports both 3.3 V and 5 V operation and delivers a 117.6 MHz maximum internal frequency with a 16.6 ns propagation delay, making it suitable for glue logic, bus interfacing, and state-machine implementations. The MAX 9000 architecture uses a CMOS EEPROM process that provides non-volatile configuration, eliminating the need for external boot PROMs required by SRAM-based FPGAs. This instant-on behavior is critical in systems where the logic must be operational within microseconds of power-up, such as industrial control backplanes and telecommunications line cards. Typical applications include PCI bus bridging, ISA/EISA bus interfacing, high-speed address decoding, DMA control, and legacy system glue logic. The 240-pin RQFP package with 0.5 mm terminal pitch provides 187 I/O pins for wide bus applications. When designing with this device, note that the MAX 9000 family is a mature, legacy product line. Verify availability and consider MAX II or MAX V CPLDs for new designs requiring lower power and smaller packages. The EPM9560RC240-15C remains in demand for maintenance and repair of existing equipment. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for sourcing and replacement decisions.
EPM9560RC240-15N - MAX 9000 CPLD, 560 Macrocells, 15ns, RQFP-240
The Intel (formerly Altera) EPM9560RC240-15N is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the third-generation MAX 9000 family, featuring 560 macrocells, 12,000 usable gates, and 216 maximum user I/O pins in a 240-pin RQFP package. The device operates at a 15 ns pin-to-pin propagation delay (tPD) and a 145 MHz internal counter frequency (fCNT), delivering deterministic logic integration for high-density glue-logic, bus-interface, and state-machine designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-backed programmable logic device that sits hierarchically between simple SPLDs (e.g., GAL/PAL) and FPGAs. CPLDs are characterized by deterministic timing, instant-on behavior, high pin counts, and very low power consumption in standby, making them the preferred choice for system-level address decoding, bus arbitration, peripheral control, and power-sequencing logic. The MAX architecture walks up the taxonomy as: macrocell -> Logic Array Block (LAB) -> CPLD -> programmable logic -> semiconductor device. Key features of the EPM9560RC240-15N include 35 Logic Array Blocks (LABs), 5.0 V in-system programmability (ISP) via IEEE 1532/JTAG, JTAG boundary-scan test support, open-drain or programmable I/O standards, and a commercial operating-temperature range of 0C to 70C. The non-volatile EEPROM configuration cell removes the need for external boot PROMs, enabling single-chip designs with instant-on functionality at system power-up. Architecturally, the MAX 9000 device uses a continuous interconnect network called the Programmable Interconnect Array (PIA), which routes every LAB to every other LAB through a uniform, predictable switch matrix. Combined with the EEPROM process node, this delivers 100% interconnect utilization with no contention, predictable tPD regardless of design placement, and true pin-locking that survives design iterations without re-routing PCB traces. Typical applications of the EPM9560RC240-15N include 32-bit/64-bit microprocessor peripheral decoding (PCI, VME, ISA), high-speed state-machine controllers, bus arbiters and protocol bridges, industrial PLC I/O expansion, and legacy glue-logic replacement. The wide I/O count (216 pins) supports designs requiring many chip-select, interrupt, or peripheral-control signals. Designers should note that the EPM9560RC240-15N is an NRND/EOL-era part; production status should be confirmed with the manufacturer. For new designs, the MAX II or MAX V CPLD families are recommended; pin-compatible drop-in alternatives within the MAX 9000 family (same RQFP-240 footprint) include the speed-grade and temperature-grade variants EPM9560RC240-15, EPM9560RC240-12, and EPM9560RC240-10N. This page synthesizes distributor pricing, drop-in same-footprint alternatives from the Site MPN list, and practical design notes not found in the manufacturer datasheet alone, providing engineers and procurement teams with a single consolidated reference.
EPM9560RC240-15W - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560RC240-15W is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 191 user I/O pins in a 240-pin RQFP (PowerQuad) package. It operates from a 5.0 V supply (4.75 V to 5.25 V) with a 15 ns pin-to-pin propagation delay and supports in-system programmability (ISP) via an EEPROM-based configuration element. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. In the broader hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, making it the preferred choice for glue logic, bus interfacing, and state machines. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated in advanced CMOS with EEPROM configuration cells. Key differentiators of the EPM9560RC240-15W include its 560 macrocells (the highest density in the MAX 9000 family), 12,000 usable gates, 191 user I/O pins, and a 15 ns pin-to-pin delay. The device supports 5.0 V in-system programmability, allowing field reconfiguration without removing the part from the board. Its EEPROM-based architecture retains configuration without external boot memory, unlike SRAM-based FPGAs. The MAX 9000 architecture uses a hierarchical interconnect scheme with logic array blocks (LABs) and a programmable interconnect array (PIA), delivering predictable, deterministic timing. Counter speeds reach up to 117.6 MHz to 144 MHz depending on speed grade. The 240-pin RQFP package with exposed pad provides a compact surface-mount footprint for high-I/O-count designs. Typical applications include industrial control glue logic, bus bridging and protocol conversion, legacy system replacement, test and measurement instrumentation, telecommunications line cards, and military/aerospace systems requiring long-term supply and non-volatile configuration. When designing with the EPM9560RC240-15W, ensure all VCC pins are decoupled with 0.1 uF ceramic capacitors placed close to the device, and provide a clean 5.0 V rail within the 4.75 V to 5.25 V range. The JTAG ISP interface requires a 10-pin header and proper pull-up resistors on TCK, TMS, TDI, and TDO. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for selection, replacement, and layout decisions.
EPM9560RC240-15YY - MAX 9000 CPLD 560 Macrocells | Intel | 240-RQFP
The Intel EPM9560RC240-15YY is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, integrating 560 macrocells, 12,000 usable gates, and 191 user I/O pins in a 240-pin RQFP (Plastic Quad Flat Pack) surface-mount package. It features a typical propagation delay (tpd) of 15 ns and a maximum internal operating frequency of 117.6 MHz at 5 V VCC, making it one of the high-density members of the MAX 9000A series. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style AND/OR arrays with a central interconnect matrix. Within the broader taxonomy it sits as a sibling to the FPGA (Field-Programmable Gate Array); CPLDs are deterministic, low-power, and pin-for-pin predictable, while FPGAs are LUT-based and higher density. CPLDs belong to the family of programmable logic devices, which themselves are a sub-category of digital semiconductors used for glue logic, bus interfacing, and state-machine replacement. Key features include in-system programmability via the IEEE 1149.1 (JTAG) interface, a 5.0 V single-supply core, pin-compatible speed-grade options (-10, -12, -15), and MultiVolt I/O supporting mixed 5 V / 3.3 V signalling. The MAX 9000A architecture uses Logic Array Blocks (LABs) tied together by a programmable interconnect array (PIA), providing deterministic 15 ns pin-to-pin timing across all 560 macrocells with no routing-induced jitter. Typical applications include high-speed glue logic for 32-bit microprocessors, bus arbitration and interface bridging (PCI, ISA, VME), peripheral controllers, and digital state-machine replacement in telecommunications and industrial control. The wide 191-I/O count also suits multi-channel buffer/driver consolidation and large address-decoder functions. When designing with this device, observe the 5 V VCC requirement and ensure JTAG chain integrity if multiple devices are cascaded. Decoupling requires 0.1 uF ceramic capacitors close to each VCC/GND pair, with a bulk tantalum or ceramic capacitor on each supply plane. Programming uses the IEEE 1149.1 boundary-scan chain and is supported by Altera/Intel Quartus and legacy MAX+PLUS II tools. This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 9000 family, and practical design notes not collected in any single manufacturer document.
EPM9560RC240-1O - MAX 9000 CPLD, 560 Macrocells, 216 I/O, RQFP-240 | Altera
The Altera (Intel) EPM9560RC240-1O is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates, 560 macrocells, and 35 Logic Array Blocks (LABs) in a 240-pin RQFP package. It features 216 user I/O pins, an internal frequency of 145 MHz, and a pin-to-pin propagation delay of approximately 12 ns at 5V supply, with the "-1O" suffix denoting the industrial operating temperature grade of -40C to +85C per Altera's MAX 9000 family nomenclature. The device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which provides predictable, deterministic timing through a uniform interconnect scheme and is in-system programmable via IEEE 1149.1 JTAG. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with the density of small FPGAs, sitting in the broader taxonomy of programmable logic devices (PLD) alongside simple PLDs (SPLD), FPGAs, and structured ASICs. CPLDs are typically used for glue logic, bus interfacing, state machines, and power-up sequencing where instant-on (no boot PROM) and deterministic timing are required. Compared with FPGAs, CPLDs offer lower density but faster, fixed-input-to-output delays that are independent of routing, making the EPM9560RC240-1O well suited to high-fan-in decoder and address-decoding tasks. Key features include 4.8 ns clock-to-output (tCO) delay, 3.0 ns global setup time, 5V tolerant I/O, and the 240-pin RQFP (Reduced-height Quad Flat Pack) surface-mount package. The MAX 9000 family is fabricated on a 0.65 um CMOS EEPROM process, allowing 100% in-system programmability for rapid prototyping and field upgrades. The EPM9560RC240-1O is the lower-cost industrial-temperature variant of the EPM9560RC240 family, distinguished from the -15, -20 speed grades only by the device timing bin and the operating temperature suffix. Typical applications for the EPM9560RC240-1O span telecommunications backplane glue logic, industrial control board-level integration, peripheral bus decoding (PCI, VME, ISA), memory-address decoding, DRAM controller interfaces, and high-density state-machine replacement for discrete 7400-series logic. Designers often choose the MAX 9000 family when they need high I/O count, 5V operation, and instant-on behavior without an external configuration memory. When designing with the EPM9560RC240-1O, ensure the PCB has sufficient thermal copper area for the RQFP-240 package and that signal integrity is preserved on the high-speed 144 MHz I/O paths. Designers should follow Altera's JTAG programming guidelines (ByteBlaster or BitBlaster) and respect the 5V VCCIO tolerance when interfacing to mixed-voltage peripherals. Because the MAX 9000 family is in mature production status, lead times and lifecycle should be confirmed with the supply chain before new design starts.
EPM9560RC240-2 - MAX 9000 CPLD, 560 Macrocells, 240-RQFP | Altera
The Altera EPM9560RC240-2 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, providing 12,000 usable gates and 560 macrocells in a 240-pin RQFP package. It is a 5V in-system programmable logic device featuring a pin-to-pin propagation delay of 2 ns (the "-2" speed grade) and supports system frequencies up to 100 MHz, making it suitable for high-performance glue-logic, bus-interface, and state-machine designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL devices with the density of small FPGAs. Within the broader semiconductor taxonomy, the EPM9560RC240-2 sits as: CPLD -> programmable logic device -> logic IC -> integrated circuit -> semiconductor. MAX 9000 series devices use a classic EEPROM-based non-volatile architecture that retains configuration without external boot memory, contrasting with SRAM-based FPGAs that require a configuration PROM. CPLDs are widely used for deterministic, single-cycle propagation-delay logic where predictable timing and instant-on behavior are required. The EPM9560RC240-2 integrates 560 macrocells organized in Logic Array Blocks (LABs) with a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR array, a configurable flip-flop, and dedicated I/O. The device offers 212 user I/O pins, in-system programmability via JTAG (IEEE Std 1149.1), and supports 5V tolerant I/O with multi-voltage I/O standards including 3.3V and 5V operation. The "-2" suffix indicates the fastest speed grade in the family, offering 2 ns pin-to-pin delay. Typical applications include bus-interface bridging, address decoding, peripheral control glue logic, state-machine controllers, and high-speed interface adaptation. The 240-pin RQFP (Metric Quad Flat Pack) package provides ample I/O for multi-bus bridging applications while remaining hand-solderable for prototypes. When designing with the EPM9560RC240-2, ensure the 5V supply is well decoupled with 0.1uF ceramic capacitors near each VCC pin, and that the JTAG programming header follows the IEEE 1149.1 standard pinout. The device is non-volatile, so designers should review the Quartus/MAX+PLUS II programming flow before committing to a board layout.
EPM9560RC240-20 - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
The Intel (formerly Altera) EPM9560RC240-20 is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells and 191 user I/Os in a 240-pin RQFP (240-BFQFP with exposed pad) package, with a -20 speed grade (tPD max = 20 ns). Built on a third-generation Multiple Array MatriX (MAX) architecture, this device combines high-performance CMOS EEPROM technology with 12,000 usable gates and 35 logic array blocks, making it suitable for high-density glue-logic, bus-interface, and state-machine designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that occupies the middle ground between discrete PAL/GAL devices and high-density FPGAs. Within the programmable logic taxonomy, CPLDs sit alongside FPGAs under the broader category of Programmable Logic Devices (PLDs). MAX 9000 devices are particularly valued for their deterministic timing, predictable pin-to-pin delays, and 5V tolerant I/O - characteristics that legacy industrial designs often require. Key features include 4.75V to 5.25V single-supply operation, a 100 MHz maximum internal frequency, in-system programmability via IEEE Std 1149.1 (JTAG) and Altera's proprietary programming interfaces, and a commercial operating temperature range of 0C to 70C. The 240-pin RQFP package provides a thermal resistance of approximately 22 C/W (junction-to-ambient, typical) and a 31.0 mm x 31.0 mm body suitable for socketed or surface-mount legacy boards. JTAG boundary-scan support simplifies board-level testability. Architecturally, the MAX 9000 family uses a uniform interconnect architecture called the Programmable Interconnect Array (PIA), which routes signals between the 35 Logic Array Blocks (LABs) and the I/O elements. Each LAB contains 16 macrocells; the 560-macrocell density allows designers to integrate wide address decoders, register-rich state machines, and asynchronous glue logic in a single chip, replacing multiple 22V10/16V8-style PALs and 74LS discrete glue. Typical applications include legacy industrial control boards, telecommunications backplane glue logic, PCI/ISA bus interface bridges, and bus-width translation/muxing on legacy microcomputer systems. The 5V-tolerant I/Os also suit retrofit designs where modern 3.3V-only FPGAs would require level shifters. When designing with the EPM9560RC240-20, verify that the JTAG chain order and I/O assignments match the legacy schematic; the 240-RQFP footprint is shared across many MAX 9000 variants, so pin-compatible migration within the family is straightforward. Plan for in-system programming header access to support field updates. This page synthesizes distributor pricing, pin-compatible MAX 9000 alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC240-20C - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
The Altera EPM9560RC240-20C is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 12,000 usable gates, 560 macrocells, and 216 maximum user I/O pins in a 240-pin RQFP package, operating from a 5.0 V supply with a 20 ns pin-to-pin propagation delay. It is a high-performance CMOS EEPROM-based programmable logic device built on Altera's third-generation Multiple Array MatriX (MAX) architecture. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on characteristics of a PAL. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. The MAX 9000 family uses EEPROM configuration cells, so the EPM9560RC240-20C retains its configuration without an external boot PROM and is live within microseconds of power-up. Key features include 560 macrocells organized into 35 logic array blocks (LABs), 12,000 usable gates, 216 maximum user I/O pins, a 20 ns pin-to-pin propagation delay (tPD1), and a 144 MHz internal counter frequency (fCNT). The device supports 5.0 V in-system programmability (ISP) and is specified for 0 C to 70 C commercial operation. The MAX 9000 architecture routes signals through a programmable interconnect array that feeds 35 LABs, each containing 16 macrocells with individual product-term allocation. This architecture delivers deterministic, predictable timing - a critical advantage over SRAM-based FPGAs for glue-logic, bus-interface, and state-machine functions where worst-case delay must be guaranteed. Typical applications include PCI and ISA bus bridging, memory controller glue logic, industrial control state machines, telecommunications line-card logic, and legacy system replacement where 5 V logic levels and instant-on operation are required. When designing with the EPM9560RC240-20C, note that it is a 5.0 V-only device and is not 3.3 V tolerant on all pins; level shifting is required when interfacing to modern 3.3 V or 1.8 V logic. The 240-pin RQFP package requires careful thermal and signal-integrity planning at 144 MHz. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for replacement and redesign decisions.
EPM9560RC240-20N - MAX 9000 CPLD 560 Macro 240-RQFP | Altera
The Altera EPM9560RC240-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 560 macrocells, 12,000 usable gates, and 216 maximum user I/O pins, housed in a 240-pin RQFP (PowerQuad/plastic quad flat pack) package. It operates from a 5.0 V supply with a 20 ns pin-to-pin propagation delay (tPD1) and a 144 MHz internal counter frequency. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL/PLD. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: PLD -> CPLD -> FPGA -> programmable logic device. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM configuration cells that retain their programmed state without external configuration memory. Key features of the EPM9560RC240-20N include 560 macrocells organized into 35 logic array blocks (LABs), 12,000 usable gates, 216 user I/O pins, and 5.0 V in-system programmability (ISP). The EEPROM-based configuration provides instant-on operation, eliminating the boot delay and configuration PROM required by SRAM-based FPGAs. The 20 ns speed grade (-20) delivers 144 MHz counter performance and 3.0 ns flip-flop setup time (tSU). The MAX 9000 architecture uses a continuous interconnect array that provides deterministic, uniform pin-to-pin timing independent of routing, which simplifies static timing analysis compared with segmented FPGA routing. Each macrocell contains a programmable flip-flop with individual clock, clear, and preset control, allowing mixed sequential and combinatorial logic in a single device. Typical applications include glue logic consolidation, bus bridging and protocol conversion, address decoding, state machines, and legacy system replacement where 5.0 V logic levels and instant-on operation are required. The 240-pin RQFP package provides 216 I/O for wide bus interfaces. When designing with this device, note that the -20 speed grade is the slowest MAX 9000 grade; timing-critical paths should be verified against the 20 ns tPD1 and 3.0 ns tSU limits. The 5.0 V core also requires level shifting when interfacing with modern 3.3 V or 1.8 V logic. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migration decisions.
EPM9560RC240-3 - MAX 9000 CPLD 560 Macrocell | Altera
The Altera EPM9560RC240-3 is a MAX 9000 series Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 3 ns pin-to-pin propagation delay, housed in a 240-pin RQFP (PowerQuad II) package. It operates from a 5 V supply and provides 192 user I/O pins for high-density glue logic, bus interfacing, and state machine implementations. A CPLD (Complex Programmable Logic Device) is a programmable logic IC built from non-volatile EEPROM cells that retain configuration without external memory. Within the logic IC hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers fewer logic resources than an FPGA but delivers deterministic, single-cycle timing and instant-on operation. The MAX 9000 family extends this architecture to FPGA-like densities using multiple Logic Array Blocks (LABs) interconnected by a fast, predictable routing matrix. The EPM9560RC240-3 delivers 560 macrocells organized into 20 LABs, each containing 16 macrocells with individual product-term logic. Its 3 ns pin-to-pin delay (speed grade -3) supports synchronous interfaces up to approximately 150 MHz, while the 5 V core and I/O simplify direct interfacing to legacy TTL and CMOS buses without level shifters. The 240-pin RQFP package provides 192 I/O pins, enabling wide address/data bus decoding in a single device. Architecturally, the MAX 9000 uses EEPROM-based configuration, giving the device instant-on capability and high immunity to single-event upsets compared with SRAM-based FPGAs. The multi-LAB structure with a programmable interconnect array (PIA) provides deterministic routing delays, which simplifies static timing analysis for critical control paths. Typical applications include PCI and ISA bus bridging, telecommunications line-card control, industrial automation controllers, and legacy system glue logic where 5 V signaling and non-volatile configuration are required. The device is widely used as a replacement for discrete 74-series logic and older PAL devices in long-lifecycle industrial and telecom equipment. When designing with the EPM9560RC240-3, note that the 5 V core draws significant quiescent current and requires adequate decoupling on every VCC pin. Because the part is obsolete, designers should verify availability and consider pin-compatible MAX 9000 speed-grade variants or migration to modern CPLDs for new designs. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, providing a single reference for engineers maintaining or sourcing this legacy CPLD.
EPM9560RC28-15 - MAX 9000 CPLD 560 Logic Elements 15ns 5V | Altera
The Altera EPM9560RC28-15 is a member of the MAX 9000 family of high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on Altera's third-generation Multiple Array MatriX (MAX) architecture, housed in a 28-pin ceramic windowed DIP-style RC package. It integrates approximately 6,000 usable gates and 560 logic elements in a single in-system programmable device with a 15ns pin-to-pin propagation delay (tPD). The device supports 5.0V in-system programmability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, enabling rapid prototyping and field upgrades without removing the part from the board. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EEPROM-based programmable logic device that combines the deterministic timing of classic PLDs with higher logic density and interconnect flexibility. In the broader system hierarchy, a CPLD sits between a small FPGA and discrete TTL/CMOS glue logic, providing predictable propagation delays, instant-on behavior at power-up (no boot PROM required), and excellent pin-locking capability for multi-voltage I/O bridging. The MAX 9000 family is positioned as the high-density workhorse of the classic Altera MAX series, sitting above MAX 7000 and below early Cyclone FPGAs in capability. Key features of the EPM9560RC28-15 include 212 macrocells, 16 logic array blocks (LABs), a maximum of 212 user I/O pins in the largest package, and 5V tolerant I/O cells supporting both 3.3V and 5V interfaces via programmable drive strengths. The device also provides JTAG boundary-scan test capability conforming to IEEE 1149.1, four user-defined I/O banks for mixed-voltage designs, and global control signals with programmable inversion. The 15ns speed grade makes it suitable for control logic, bus decoding, and address decoding in legacy 5V systems. The MAX architecture uses a Logic Array Block (LAB) matrix with continuous interconnect channels (called the Programmable Interconnect Array, or PIA) and an I/O block architecture that supports registered, latched, or combinational I/O with programmable output enables. Each macrocell contains a programmable AND/OR array, a flip-flop, and a programmable clock/clear configuration, allowing designers to implement complex combinatorial and sequential logic in a deterministic fashion. The EEPROM-based configuration cell ensures instant-on behavior with no external boot device required. Typical applications include bus interface bridging, peripheral controller glue logic, address decoding and DMA control in industrial and telecom backplane designs, legacy 5V system logic replacement, automotive body electronics, and military/aerospace systems (the -15 speed grade and RC ceramic package indicate high-reliability / military temperature range). The EPM9560RC28-15 is also well-suited to ASIC prototyping, test equipment front-ends, and any system that requires deterministic 15ns timing with non-volatile configuration. When designing with this device, note that the RC-28 suffix indicates a 28-pin ceramic windowed DIP package with the speed grade -15. The window allows ultraviolet erasure of the EEPROM array for reuse during prototyping. Engineers should provide a clean 5V ±5% supply and follow Altera's MAX 9000 JTAG programming guidelines for in-system configuration. This part is mature; consult Altera's PDN archive for current lifecycle status before new designs. This page synthesizes verified distributor data, package-level pinout detail, drop-in alternatives from the MAX 9000 family, and practical design notes not found on the manufacturer datasheet summary page.
EPM9560RC304-10 - MAX 9000 CPLD, 560 Logic Elements | Intel
The Intel (Altera) EPM9560RC304-10 is a high-density CMOS erasable programmable logic device (EPLD) from the MAX 9000 family, packaged in a 304-pin RQFP (RC) carrier with 12 ns pin-to-pin propagation delay. It delivers 560 macrocells / 16,000 usable gates and operates from a 5 V supply with in-system programmability through JTAG. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic device that combines the deterministic timing of PAL/GAL architecture with the density of an FPGA. In the system hierarchy, the EPM9560RC304-10 sits at the complex programmable logic tier, above simple PLDs (PAL/GAL), below low-density FPGAs, and parallel to other MAX 9000 family members. It serves as glue logic, bus interface, and state-machine fabric in systems where deterministic 12 ns timing and instant-on non-volatile configuration are required. Key features include 304 user I/O pins, JTAG-compliant IEEE 1149.1 boundary-scan support, pin-compatible speed grades (-10, -12, -15, -20), 5 V tolerant I/O with 3.3 V PCI-compatible variants, and 100% stuck-fault coverage via JTAG. The MAX 9000 architecture uses a global interconnect matrix that delivers predictable, fixed propagation delays regardless of placement or routing, simplifying timing closure. The device employs a 0.65 µm CMOS EEPROM process with non-volatile configuration cells, allowing instant-on operation without external boot memory. Multiple Logic Array Blocks (LABs) of 16 macrocells each are stitched together through a programmable interconnect array (PIA), and each macrocell contains a programmable flip-flop with product-term or D flip-flop mode. Typical applications include bus-interface bridging in telecom backplanes, peripheral glue logic for PowerPC and Pentium-era processor systems, address decoding for ISA/PCI/VME buses, and high-performance state-machine controllers in industrial automation. The 560-macrocell density makes it well suited to replace multiple discrete PAL/GAL devices with a single footprint. When designing with the EPM9560RC304-10, observe the 5 V VCC tolerance window and ensure decoupling capacitors (0.1 µF plus 10 µF bulk) are placed within 5 mm of every VCC/GND pair. Boundary-scan testing through the JTAG pins is recommended for production test access. This page synthesizes distributor pricing, MAX 9000 family cross-reference, and design notes for the EPM9560RC304-10 that are not available in the original Altera MAX 9000 datasheet alone.
EPM9560RC304-15 - 560-Macrocell MAX CPLD, 15ns | Altera / Intel
The Altera (now Intel Programmable Solutions Group) EPM9560RC304-15 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, integrating 560 macrocells in a 304-pin RQFP (plastic Quad Flat Pack) package with a 15 ns pin-to-pin propagation delay. The device is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which combines the fine-grained architecture of traditional PLDs with the high density of FPGAs in a single, in-system-programmable package. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays on a single chip with a programmable interconnect. CPLDs sit in the broader hierarchy: programmable logic -> programmable logic device -> CPLD -> MAX architecture -> non-volatile logic. Unlike SRAM-based FPGAs, the EPM9560RC304-15 retains its configuration in on-chip EEPROM and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, eliminating the need for a separate programmer and enabling field upgrades. Key features include 560 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, a 15 ns combinatorial propagation delay (tPD), and a maximum operating frequency that supports high-speed glue-logic and bus-interface applications. The 5.0-V tolerant I/O and PCI-compliant drive capability allow direct interfacing with 5-V TTL logic and PCI bus signals without external buffering. Typical applications include high-speed address decoding and bus arbitration, complex state-machine controllers, interface bridging between microprocessors and peripherals, and PCI bus target devices. Designers commonly pair the EPM9560RC304-15 with synchronous SRAM, microcontrollers, and DMA controllers in industrial automation, telecommunications, and embedded computing designs. When designing with this part, pay close attention to the I/O pin count (212 user I/Os across 304 pins leaves 92 pins for power, ground, JTAG, and dedicated inputs) and ensure proper decoupling on all VCCINT and VCCIO rails. Use the JTAG interface for both ISP and boundary-scan testing to streamline manufacturing test flow. This page synthesizes distributor inventory, drop-in alternative listings, and design notes not found in the original MAX 9000 datasheet to accelerate sourcing and board bring-up.