FPGA & CPLD
Products (6352)
EPM9560GI280-20 - 560 Macrocell EE PLD, 280-Pin PGA | Intel/Altera
The Intel/Altera EPM9560GI280-20 is a high-density CMOS EEPROM-based Programmable Logic Device (PLD) from the MAX 9000 device family, delivering 560 macrocells, 216 I/O lines, and 772 flip-flops in a 280-pin Pin Grid Array (PGA) package. The "-20" speed grade denotes a 20 ns pin-to-pin delay, and the "GI" package code identifies the ceramic PGA industrial-temperature variant. A Programmable Logic Device (PLD) is a general-purpose digital integrated circuit whose internal logic and interconnect are defined by the user after manufacturing, allowing one silicon device to implement a wide range of glue logic, state machines, bus interfaces, and datapath controllers. The MAX 9000 family is built on a third-generation Multiple Array MatriX (MAX) architecture that combines fine-grained Logic Array Blocks (LABs) with an EEPROM programming technology, providing non-volatile configuration that retains state across power cycles without an external boot PROM. Key features of the EPM9560GI280-20 include 12,000 usable gates, 560 macrocells, 216 user I/O pins, 772 flip-flops, an in-system programmability (ISP) interface compliant with IEEE Std. 1149.1 (JTAG), and a 5.0 V VCC core supply. The device is supported by the Altera MAX+PLUS II development system, which offers schematic, VHDL, Verilog HDL, and AHDL design entry together with synthesis, simulation, timing analysis, and device programming. The MAX 9000 architecture arranges 560 macrocells into 28 LABs of 16 macrocells each, with a continuous FastTrack interconnect running across the chip. Each macrocell contains a programmable-AND/fixed-OR array, an XOR gate for polarity control, a programmable register with clock, clock-enable, clear, and preset controls, and an I/O architecture that supports input, output, output-enable, and bidirectional operation. The result is a flexible platform suitable for high-density glue logic, register-intensive datapaths, and bus-interface bridging. Typical applications include telecom and datacom line-card glue logic, industrial control and factory automation controllers, military and aerospace avionics, legacy bus-interface bridging, and high-density state-machine replacement of discrete 74LS/74F logic. The non-volatile EEPROM cell array makes it well suited to applications that must boot into a defined state without external configuration memory. When designing with this device, ensure that the 5.0 V VCC supply rises monotonically and that I/O pin overshoot/undershoot is limited to the datasheet's transient envelope (overshoot to 7.0 V and undershoot to -2.0 V for periods under 20 ns under no-load conditions). Designers should also verify timing closure against the 20 ns speed grade using MAX+PLUS II timing analysis. This page synthesizes distributor availability, parametric context, and drop-in alternative options for the EPM9560GI280-20 that are not consolidated in the original MAX 9000 datasheet.
EPM9560GM280-15 - 560 Macrocells MAX 9000 PLD 5V | Altera
The Altera EPM9560GM280-15 is a high-density CMOS EEPROM-based Programmable Logic Device (PLD) from the MAX 9000 family, providing 560 macrocells, 772 flip-flops, and 216 user I/O pins in a 280-ball FineLine BGA (GM) package. It operates from a nominal 5.0V supply with an absolute maximum of 5.5V and supports 3.3V or 5V I/O operation for mixed-voltage system interfacing. Background: A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the end user rather than the device manufacturer. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which combines the high density of FPGAs with the non-volatility of EEPROM storage. Within the broader taxonomy, PLDs sit under programmable logic, alongside FPGAs and CPLDs, and are used to implement glue logic, bus interfacing, and state machines without the cost of an ASIC. The 'EE' prefix indicates electrically erasable (EEPROM-based) configuration, enabling in-system programmability (ISP) via the IEEE Std 1149.1 JTAG interface. Key features include 560 macrocells, 216 programmable I/O pins, 5V in-system programmability through JTAG, and a 15ns pin-to-pin propagation delay (the '-15' speed grade). The device is implemented in 0.35 µm CMOS EEPROM technology, retains its configuration without external memory, and supports MultiVolt I/O for seamless interfacing between 5V and 3.3V logic domains. Boundary-scan testability is provided through full JTAG (IEEE 1149.1) compliance. Architecturally, the MAX 9560 organises logic into Logic Array Blocks (LABs) of 16 macrocells each, interconnected by a programmable interconnect array. Each macrocell contains a programmable AND/OR array, a configurable flip-flop, and product-term allocation logic. The EEPROM cell stores configuration, eliminating the need for a separate boot PROM at power-up. This combination of high logic density, deterministic timing, and non-volatile storage made the MAX 9560 popular for prototyping and low-volume glue-logic replacement. Typical applications include telecommunications line cards, industrial control glue logic, bus-interface bridges (PCI, ISA, VME), and high-density state machines. The wide 216-I/O count and JTAG-based ISP made the GM280 package particularly suitable for space-constrained designs requiring live in-field reconfiguration. When designing with this device, observe the 5.5V absolute maximum supply rating and ensure JTAG chain integrity for ISP. For new designs, consider the MAX II or MAX V family as a lower-power, lower-cost modern alternative; for legacy boards, ensure firmware and Quartus support files are archived. This page synthesises distributor stock, drop-in package alternatives from the MAX 9000 family, and design notes that go beyond the manufacturer datasheet, including power estimation and JTAG programming guidance.
EPM9560R1208-20 - MAX 9000 CPLD 6k Gates 1208-pin | Altera
The Altera EPM9560R1208-20 is a member of the MAX 9000 family of high-performance, CMOS EEPROM-based programmable logic devices (PLDs) built on Altera's third-generation Multiple Array MatriX (MAX) architecture. The device provides 6,000 usable gates, a 20 ns propagation delay grade, and is housed in a 1208-pin R-package (R-prefix, ball-grid array) suitable for surface-mount assembly. It supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, eliminating the need for a separate programmer. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on semiconductor that integrates multiple PAL/GAL-style logic blocks with a programmable interconnect matrix. CPLDs sit between discrete logic ICs (74-series glue logic) and FPGAs in the programmable-logic hierarchy, providing deterministic timing, predictable I/O behavior, and instant power-on logic without external boot memory. The MAX 9000 family is widely used for decoder, counter, state-machine, bus-interface, and glue-logic applications where deterministic pin-to-pin timing is more important than raw gate count. Key features of the EPM9560R1208-20 include 560 macrocells, a maximum operating frequency of 125 MHz, 212 user I/O pins, a tPD of 20 ns, and an industrial 0C to +70C operating temperature range. The device includes a JTAG-compliant boundary-scan test interface, four dedicated input pins, global clock networks, and open-drain or programmable output structures. Power consumption is typically 200 mA at 5.0 V VCC, with low-power standby modes for battery-backed applications. Architecturally, the MAX 9000 family uses a Logic Array Block (LAB) structure composed of 16 macrocells each, interconnected by a programmable interconnect array (PIA). Each macrocell contains a programmable AND/OR/flip-flop chain, allowing implementation of sum-of-products combinatorial or registered sequential logic in a single device. The on-chip EEPROM cells retain configuration permanently without external memory. Typical applications for the EPM9560R1208-20 include bus-interface bridging, address decoding, FIFO control, glue logic for microprocessor systems, peripheral interface adaptation, and high-density state-machine replacement. The 1208-ball package is suitable for high-I/O-count designs where many signal pins must be brought off-chip simultaneously. Compared to FPGAs in the same era, MAX 9000 devices offer instant-on behavior and deterministic timing ideal for control-path logic. When designing with the EPM9560R1208-20, ensure that the 5.0 V supply is well decoupled with 0.1 uF and 10 uF capacitors placed close to the VCC pins. Use the JTAG pins (TCK, TMS, TDI, TDO, and TRST) for in-system programming and boundary-scan test, and follow Altera's recommended PCB layout for fine-pitch BGA packages to maintain signal integrity at high toggle rates. This page synthesizes distributor stock, Altera MAX 9000 family datasheet extracts, and drop-in compatible CPLD variants from the EPM9560 series - practical sourcing and engineering data not consolidated on any single manufacturer or distributor page.
EPM9560RC-10 - MAX 9000 CPLD, 560 Macrocells, 240-pin PGA | Intel
The Intel (formerly Altera) EPM9560RC-10 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, featuring 560 macrocells, approximately 12,000 usable gates, and a 10 ns pin-to-pin propagation delay. It is housed in a 240-pin ceramic Pin Grid Array (PGA) package designated by the 'RC' suffix and operates over the commercial 0C to +70C temperature range. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells on a single chip, providing deterministic timing and instant-on behavior. Within the broader programmable logic hierarchy, the MAX 9000 series sits between classic PLDs (PAL/GAL) and FPGAs, offering glue-logic integration, bus decoding, state-machine encoding, and peripheral interface bridging. It is part of the wider semiconductor category of programmable logic ICs, which includes CPLDs, FPGAs, and SPLDs. Key features of the EPM9560RC-10 include 16 Logic Array Blocks (LABs) interconnected by the third-generation Multiple Array Matrix (MAX) programmable interconnect, 212 user I/O pins, 5.0 V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, and built-in boundary-scan test support. The architecture supports each macrocell with up to 32 product terms and a programmable register, enabling efficient implementation of wide combinational and registered logic functions. Typical applications include high-performance bus-interface bridging, processor glue logic, peripheral controllers, and state-machine implementation in telecommunications, industrial automation, and military/aerospace systems. The 240-pin PGA package also makes the EPM9560RC-10 a strong fit for prototyping and through-hole industrial backplane designs where socketed replacement is preferred over surface-mount rework. When designing with this device, observe the maximum I/O current ratings and provide proper decoupling on every VCCINT and VCCIO pin pair. The device is non-volatile, so configuration is loaded at power-up with zero boot latency, which simplifies board-level power sequencing compared with SRAM-based FPGAs.
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
The Altera (now Intel) EPM9560RC-15 is a high-density 560-macrocell Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 12,000 usable gates, 191 I/O pins, and a pin-to-pin propagation delay of 15 ns, housed in a 240-pin RQFP (32x32 mm) package. The device is built on the third-generation Multiple Array MatriX (MAX) architecture with CMOS EEPROM-based configuration cells, providing 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with multi-macrocell logic blocks interconnected by a central programmable switch matrix. CPLDs sit in the broader programmable logic hierarchy: CPLD -> programmable logic -> logic IC -> semiconductor. They are typically chosen for glue logic, bus interfacing, state-machine control, and power-up deterministic logic that must initialize without external boot memory. Compared with SRAM-based FPGAs, CPLDs are non-volatile, boot instantly, and consume far less dynamic power for small to medium logic densities. Key features of the EPM9560RC-15 include 16 Logic Array Blocks (LABs) of 40 macrocells each, a Programmable Interconnect Array (PIA) that delivers predictable fixed-delay signal routing, 5.0-V tolerant I/O with PCI-compatible drive options, and 4.75V-5.25V (5V nominal) VCC operation. The 15-ns tPD1 makes the device suitable for moderate-speed control logic, address decoding, and asynchronous interfaces running up to approximately 66 MHz internally. Typical applications include high-pin-count bus interface bridging, address decoding and chip-select generation for microprocessors/DSPs, peripheral glue logic in industrial control, and 5V-tolerant PCI bus interface adapters. The 240-RQFP exposed-pad package supports surface-mount assembly on standard 1.6 mm PCBs with conventional forced-air cooling. When designing with this device, allocate at least one dedicated JTAG chain for ISP and boundary-scan, and provide a clean 5.0V rail with 100 nF + 10 uF decoupling near each VCC pin pair. The EPM9560RC-15 is mature/EOL - source through franchised distributors or verified aftermarket channels and validate programming via MAX+PLUS II or Quartus (legacy) software. This page synthesizes distributor pricing, parametric context, drop-in alternatives, and design notes not typically consolidated in the legacy datasheet.
EPM9560RC-304 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera
The Altera EPM9560RC-304 is a high-density member of the MAX 9000 family of CMOS EEPROM-based Complex Programmable Logic Devices (CPLDs), delivering 12,000 usable gates, 560 macrocells, and 772 flip-flops in a 304-pin RQFP (PQFP) surface-mount package. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, CPLDs belong to programmable logic devices (PLDs), which sit alongside FPGAs as the two main classes of user-programmable digital semiconductors. CPLDs are typically chosen over FPGAs for glue-logic, bus-interface, state-machine, and power-up deterministic applications because of their deterministic timing, non-volatile configuration, and instant-on behavior. Key features of the EPM9560RC-304 include 216 user I/O pins, a maximum operating frequency of 117.6 MHz (for the -15 speed grade), a propagation delay of approximately 15 ns at the -15 grade (13.4 ns for the -12 grade), and dual 3.3 V / 5 V I/O support through MultiVolt I/O pins. The device is housed in a 304-pin Power Quad Flat Pack (RQFP/PQFP-G304) with a JEDEC JESD-30 code of S-PQFP-G304, and operates over the commercial temperature range. The MAX architecture partitions logic into Logic Array Blocks (LABs), each containing 16 macrocells, and connects them through the programmable interconnect array (PIA). This design delivers predictable, pin-to-pin propagation delays that are independent of routing complexity, a key advantage over SRAM-based FPGAs in timing-critical control applications. The 5.0-V ISP and JTAG chain compliance simplify board-level bring-up and field updates. Typical applications include high-density glue logic, bus bridging and interface translation, peripheral controllers in telecom and networking equipment, industrial control systems, and legacy 5 V logic replacement. The wide I/O count also suits pin-intensive designs such as parallel bus arbitration, FIFO control, and address decoding. When designing with the EPM9560RC-304, ensure the PCB footprint matches the 304-pin RQFP land pattern (typically 1.0 mm or 0.8 mm pitch, see the package mechanical drawing) and provide a JTAG header for in-system programming. Decoupling must follow Altera's recommended 0.1 uF / 0.01 uF placement near each VCC pin group. This page synthesizes distributor pricing, drop-in same-package alternatives from the Altera MAX 9000 family, and practical design notes not found in the manufacturer datasheet alone.
EPM9560RC/ARC240 - MAX 9000 CPLD, 560 Macrocells, 240-Pin RQFP | Altera
The Altera (Intel) EPM9560RC/ARC240 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, providing 560 macrocells and up to 191 user I/Os in a 240-pin RQFP (Plastic Quad Flatpack) package. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and operates from a 5.0 V supply, supporting in-system programmability (ISP) through a dedicated JTAG/IEEE 1149.1 interface. Per the MAX 9000 datasheet, the device is specified for 12,000 usable gates with a typical internal frequency up to 144.9 MHz. A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital logic device that combines multiple PAL/PLA-like macrocell arrays on a single chip, connected through a programmable interconnect matrix. CPLDs sit in the programmable logic hierarchy between small SPLDs (a few hundred gates) and FPGAs (which offer higher density but are volatile and require an external boot PROM). Because MAX 9000 devices are EEPROM-based, they retain their configuration without an external memory and offer instant-on behavior at power-up, making them attractive for glue logic, bus interfacing, state-machine control, and address decoding in microprocessor systems. Key features of the EPM9560RC/ARC240 include 16 dedicated input pins, 4 high-speed global clock networks with programmable clock/clock-enable control, a programmable security bit for design protection, and a JTAG boundary-scan test interface compliant with IEEE Std 1149.1. The device is offered in commercial (0 C to +70 C) and industrial (-40 C to +85 C) speed grades, with propagation delays as low as 10 ns and pin-to-pin logic delays around 16 ns depending on speed grade. The MAX architecture combines the fine-grained flexibility of EPLDs with the high density of FPGAs. Each Logic Array Block (LAB) contains 16 macrocells, and each macrocell includes a programmable AND/OR/flip-flop array with selectable registered/combinatorial/feedback paths. The predictable timing model of MAX 9000 - fixed-pin, deterministic propagation delays - is the defining engineering advantage versus SRAM-based FPGAs in timing-critical control applications. Typical applications include high-performance bus decoding for 32-bit/64-bit microprocessors, peripheral glue logic, state-machine control, address demultiplexing, and interface bridging between asynchronous buses. The wide 5 V tolerance and high I/O count also make the part suitable for legacy industrial backplane designs. When designing with this device, allocate one JTAG chain for ISP and place decoupling capacitors within 100 mils of every VCC/GND pair to ensure clean power delivery to the internal EEPROM array during in-system programming.
EPM9560RC208-10 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel
The Intel (formerly Altera) EPM9560RC208-10 is a member of the MAX 9000 family of high-density Complex Programmable Logic Devices (CPLDs). It provides 560 macrocells, 16 Logic Array Blocks (LABs), and a maximum of 772 user I/O pins, all housed in a 208-pin RQFP (Plastic Quad Flat Pack) package. The "-10" speed grade indicates a pin-to-pin logic delay of 10 ns, placing it in the medium-speed tier of the MAX 9000 series. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that uses a combination of macrocells, an interconnect matrix, and an in-system programmable (ISP) configuration memory (typically EEPROM or flash). CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy, offering deterministic timing, fast power-on configuration, and high pin-to-pin performance. The MAX 9000 family specifically targets designs that need high logic density (up to 560 macrocells) combined with predictable interconnect delays. Key features of the EPM9560RC208-10 include: 560 macrocells across 16 LABs, a maximum of 212 I/O pins (208-pin package variant), 12,000 usable gates, 10 ns pin-to-pin logic delay (tPD), an in-system programmability (ISP) interface via JTAG, multiVolt I/O supporting 5.0 V / 3.3 V / 2.5 V operation, and pin-compatible migration paths within the MAX 9000 family. The device is fabricated on a 0.30 µm CMOS EEPROM process and operates from a single 5 V supply. Architecturally, the MAX 9000 series uses a deterministic FastTrack interconnect that guarantees consistent and predictable timing regardless of how a design is placed. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable I/O controls. The "-10" speed grade delivers 10 ns tPD with a 125 MHz maximum flip-flop toggle rate, suitable for bus interface glue logic, address decoding, and peripheral control rather than high-speed pipelined datapaths. Typical applications include: legacy bus interface glue logic (ISA, PCI, VME), state-machine-driven peripheral controllers, industrial machine control, instrumentation front-ends, telecom line-card glue logic, and 5 V-tolerant I/O expansion. Because the part is non-volatile (EEPROM-based), it boots in microseconds without an external configuration PROM - a key advantage over SRAM FPGAs in cold-start or fail-safe systems. When designing with this part, note that the MAX 9000 family is in mature / legacy lifecycle status. New designs should evaluate the MAX V, MAX 10, or MAX II CPLD families for lower power, smaller packages, and longer-term availability. The 208-RQFP footprint shares pinout with the EPM9560ARC208-10 (same die, lead-free finish) and the -15 / -20 speed grades, enabling easy migration between speed grades without PCB rework. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes that go beyond what the manufacturer datasheet alone offers.
EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel
The Intel (formerly Altera) EPM9560RC208-10N is a high-density CMOS EPLD from the MAX 9000 family, integrating 560 macrocells and 12,000 usable gates into a 208-pin RQFP (Power Quad Flat Pack) package with a 10 ns pin-to-pin propagation delay. It is a member of the MAX 9000 series - the second-generation MAX architecture that added second-level interconnect, FastLogic interconnect, and JTAG/IEEE 1149.1 boundary-scan support to the classic MAX 5000/7000 macrocell fabric. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays with a global interconnect matrix. Compared with FPGAs, CPLDs offer deterministic timing (predictable, fixed propagation delays), instant-on behavior from on-chip EEPROM, and typically lower power consumption for glue-logic workloads. In the broader taxonomy, CPLDs belong to programmable logic devices (PLDs) which sit alongside FPGAs, gate arrays, and standard-cell ASICs as the major silicon platforms for digital logic implementation. Key features include 153 user I/O pins, 16 logic array blocks (LABs), in-system programmability via IEEE 1149.1 JTAG, 5.0V VCCIO/VCCINT operation, and pin-to-pin logic delays of 10 ns (tPD1) corresponding to approximately 100 MHz system performance. The 208-RQFP package uses a copper-tungsten heat spreader and supports industrial temperature operation. Architecturally the device uses Altera's classic MAX macrocell with a programmable AND/OR array feeding a configurable flip-flop, plus the second-generation FastLogic interconnect that improves density and speed over the older MAX 7000. I/O pins are organized into peripheral groups sharing VCCIO banks for mixed-voltage interfacing. Typical applications include high-density bus-interface glue logic, peripheral controllers in telecom and industrial equipment, JTAG-bound production-board logic consolidation, and pin-compatible drop-in replacements for legacy 208-pin CQFP designs that have been discontinued. It is supported by legacy Altera MAX+PLUS II and Quartus design tools. When designing with the EPM9560, allocate macrocell resources per LAB carefully because the device is non-architecturally-dense by modern standards - large state machines or wide datapath functions may need to be split across multiple LABs. Designers migrating from the discontinued CQFP package should confirm RQFP land-pattern equivalence before PCB rework. This page synthesizes distributor pricing, pin-compatible MAX 9000 alternatives, and practical design notes not found in the manufacturer datasheet alone.
EPM9560RC208-12 - MAX 9000 CPLD 560 Macrocell | Altera
The Altera EPM9560RC208-12 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 772 flip-flops, and 153 user I/O lines in a 208-pin RQFP (S-PQFP-G208) package. It delivers a 12 ns pin-to-pin propagation delay and supports clock frequencies up to 125 MHz, operating from a 5 V supply with 3.3 V or 5 V I/O compatibility. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. In the broader hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs, offering non-volatile configuration, deterministic timing, and instant-on operation. MAX 9000 devices use EEPROM-based configuration, so they retain their logic after power-down without external configuration memory. Key features include 560 macrocells organized into 20 logic array blocks, 12,000 usable gates, and 153 I/O pins supporting 3.3 V or 5 V LVTTL/LVCMOS levels. The 12 ns propagation delay and 125 MHz maximum clock rate make the device suitable for glue logic, bus interfacing, and state machine implementations where predictable timing matters more than raw gate count. The MAX 9000 architecture uses a fast, predictable interconnect scheme with fixed pin-to-pin delays, unlike FPGAs where routing affects timing. Each macrocell contains a flip-flop with independent clock, clear, and preset, plus product-term logic for combinatorial functions. This architecture suits address decoding, bus arbitration, and interface bridging. Typical applications include PCI/ISA bus glue logic, industrial control state machines, telecommunications line cards, and legacy system replacement. The 5 V core with 3.3 V I/O tolerance allows direct interfacing to both legacy 5 V TTL and modern 3.3 V logic. When designing with this device, note that it is a legacy MAX 9000 part; verify availability and consider MAX II or MAX V migration for new designs. Provide adequate decoupling and observe the recommended power-up sequence. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and migration decisions.
EPM9560RC208-13 - MAX 9000 CPLD 560 Macrocell | Altera
The Altera EPM9560RC208-13 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and 208 user I/O pins, housed in a 208-pin Power Quad Flat Pack (RQFP) package. It is a 5.0 V in-system programmable EEPROM-based logic device with a 13 ns pin-to-pin propagation delay and a maximum operating frequency of 125 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. In the broader hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: it offers non-volatile configuration, deterministic timing, and instant-on operation, making it the preferred choice for glue logic, bus interfacing, and state-machine control. The MAX 9000 family extends this concept with a multi-level FastTrack Interconnect structure that delivers predictable, pin-to-pin timing independent of routing. The EPM9560RC208-13 provides 560 macrocells organized into 20 LABs (Logic Array Blocks), each containing 16 macrocells with individual product-term allocation. Its EEPROM configuration is non-volatile, so the device is operational immediately at power-up with no external configuration memory required. The 208-pin RQFP package provides 208 user I/O pins, enabling wide bus interfaces without external multiplexing. The MAX 9000 architecture uses a 5.0 V core and I/O supply, with 3.3 V and 5.0 V tolerant I/O options. The 13 ns propagation delay and 125 MHz maximum clock frequency support moderate-speed synchronous designs such as address decoding, DMA control, and peripheral glue logic. The device is programmed via the IEEE 1149.1 JTAG boundary-scan interface, which also supports in-system programming and board-level test. Typical applications include PCI and ISA bus bridging, memory controller glue logic, industrial control state machines, telecommunications line-card logic, and legacy system replacement where non-volatile, instant-on operation is required. The EPM9560RC208-13 is particularly suited to designs migrating from the 208-pin CQFP package, since Altera documents the RQFP version as form, fit, and functionally equivalent. When designing with this device, note that the MAX 9000 family is a mature, legacy product line. Designers should verify current availability and consider the MAX 7000 or MAX II families for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC208-14 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera
The Altera EPM9560RC208-14 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, delivering 12,000 usable gates and 560 macrocells in a 208-pin RQFP (Plastic Quad Flat Pack) package. It operates from a 5 V supply, supports propagation delay binning of 14 ns (pin-to-pin), and is built on a CMOS EEPROM process that delivers non-volatile configuration with in-system programmability via the JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a central interconnect matrix. In the system hierarchy, the EPM9560 sits between simple SPLDs (like classic PAL/GAL) and larger FPGAs, providing fast deterministic pin-to-pin timing, instant-on behavior (no boot PROM required), and high fan-in / fan-out glue-logic capability. The MAX 9000 family extends MAX 7000 architecture with larger Logic Array Blocks (LABs), more I/O pins, and enhanced in-system programmability (ISP) via JTAG. Key features of the EPM9560RC208-14 include 560 macrocells distributed across 16 Logic Array Blocks, 149 user I/O pins, 12,000 usable gates, and a maximum operating frequency up to 117.6 MHz. It supports 5 V and 3.3 V mixed-voltage operation on its I/O banks and is in-system programmable through the IEEE 1149.1 JTAG boundary-scan port. The -14 speed grade provides a 14 ns pin-to-pin propagation delay and a 118 MHz internal counter frequency. The device is implemented in 0.35 µm CMOS EEPROM technology with five programmable logic blocks (the MAX 9000 also adds I/O blocks for each pin), allowing design changes via the Altera MAX+PLUS II or Quartus development flows. The 208-pin RQFP package exposes dedicated JTAG, configuration, and global clock pins for design flexibility. Built-in EEPROM cells retain the design without external boot memory. Typical applications include high-density glue logic in telecommunications line cards, industrial control boards, ASIC prototyping, peripheral bus interfacing (PCI bridge logic, address decoding, bus arbitration), and replacement of multiple discrete PAL/GAL devices. The fast pin-to-pin delay also suits decoder and interrupt-controller designs where deterministic timing matters. Designers should plan for a 5 V core supply with local 0.1 µF + 10 µF decoupling near the device. The MAX 9000 architecture allows multiple MAX 9560 devices to be cascaded through the JTAG chain, supporting multi-device ISP flows. Note that newer Altera MAX V / MAX 10 CPLDs have superseded this part - the EPM9560 is generally used today for legacy design maintenance. This page synthesizes distributor stock data, parametric drop-in alternatives, and practical design guidance not found in the original MAX 9000 datasheet.
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
The Altera EPM9560RC208-15 is a MAX 9000 family EEPROM-based complex programmable logic device (CPLD) offering 12,000 usable gates and 560 macro cells with a 15 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (power quad flat pack) package operating from a 5.0 V supply. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the broader taxonomy, the EPM9560RC208-15 sits in the hierarchy CPLD -> programmable logic device (PLD) -> embedded logic IC -> semiconductor. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated on an advanced CMOS process with EEPROM configuration cells that retain their programmed state without external configuration memory. Key features include 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 560 macro cells distributed across 12 logic array blocks, and counter speeds up to 117.6 MHz. The EEPROM-based configuration provides non-volatile operation, meaning the device is live at power-up with no boot PROM or configuration controller required - a decisive advantage over SRAM-based FPGAs in glitch-sensitive or fast-boot systems. The MAX 9000 architecture integrates multiple programmable logic devices ranging from PALs, GALs, and 22V10s up to FPGA-class functions, enabling high-density integration of system-level logic. The 208-pin RQFP package provides a high I/O count for bus interfacing, glue logic consolidation, and state-machine implementation. Typical applications include legacy industrial control backplanes, telecommunications line-card glue logic, test and measurement instrumentation, and replacement of discrete 74-series logic in existing 5 V designs. Because the device is EEPROM-based, it is well suited to applications requiring deterministic power-up behavior. When designing with this device, note that the MAX 9000 family is a mature 5 V technology; verify availability and consider the MAX 7000 or MAX II families for new designs. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC208-15C - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560RC208-15C is a MAX 9000 family EEPROM-based complex programmable logic device (CPLD) with 12,000 usable gates, 560 macrocells, and 149 user I/O pins, delivering a 15 ns pin-to-pin propagation delay and 117.6 MHz counter frequency in a 208-pin RQFP package. It operates from a 5 V supply (4.75 V to 5.25 V) with 3.3 V or 5 V I/O compatibility. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks and a programmable interconnect array on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the programmable logic hierarchy, the CPLD sits between simple PLDs and FPGAs: CPLDs offer deterministic timing, non-volatile configuration, and instant-on operation, while FPGAs provide higher gate counts and more flexible routing. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, fabricated on advanced CMOS with EEPROM configuration cells. Key features include 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 560 macrocells organized into logic array blocks, and 12,000 usable gates. The EEPROM-based configuration is non-volatile, so the device retains its logic configuration through power cycles without an external configuration memory. The 15 ns speed grade supports counter speeds up to 117.6 MHz, making it suitable for glue logic, bus interfacing, and state machine implementations. The MAX 9000 architecture uses a programmable interconnect array to route signals between logic array blocks, providing predictable, fixed timing independent of routing. Each macrocell contains a flip-flop and product-term logic, enabling both combinatorial and registered functions. The 149 I/O pins support 3.3 V or 5 V operation, allowing direct interfacing with mixed-voltage systems. Typical applications include PCI bus interfaces, DSP glue logic, memory controllers, industrial control state machines, and legacy system replacement. The 5 V supply and 5 V-tolerant I/O make the device well suited to retrofitting older 5 V designs where modern low-voltage CPLDs would require level shifting. When designing with this device, note that the 208-pin RQFP package requires careful PCB layout for the JTAG chain and power decoupling. Because the part is a legacy MAX 9000 device, designers should verify lifecycle availability and consider pin-compatible speed-grade variants for supply continuity. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for sourcing and designing with the EPM9560RC208-15C.
EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
The Intel (formerly Altera) EPM9560RC208-15N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, offering 12,000 usable gates and 560 macrocells in a 208-pin RQFP package. It is built on the third-generation Multiple Array MatriX (MAX) architecture and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. The -15 speed grade corresponds to a 15 ns pin-to-pin logic delay, enabling a maximum internal operating frequency of approximately 117.6 MHz in pipelined designs. A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that sits between small SPLDs/PLDs and large FPGAs in the programmable logic taxonomy (SPLD -> CPLD -> FPGA -> programmable logic -> semiconductor). CPLDs are characterized by deterministic timing (predictable, fixed propagation delays), low static power consumption, and flash/EEPROM-based configuration that retains the bitstream without an external boot memory, making them ideal for glue logic, bus interfacing, power-up sequencing, and high-speed control planes. The MAX architecture arranges macrocells in Logic Array Blocks (LABs) interconnected by a programmable switch matrix called the Programmable Interconnect Array (PIA), giving the EPM9560 family its signature combination of high I/O count and predictable timing. Key features of the EPM9560RC208-15N include 560 macrocells, 212 user I/O pins (in this 208-RQFP variant), a 15 ns tPD (pin-to-pin delay), 117.6 MHz maximum internal frequency, 5.0 V core operation, and JTAG/IEEE 1149.1 boundary-scan test support. The device is offered in a 208-pin Power Quad Flat Pack (RQFP/BQFP) package suitable for socketed or surface-mount legacy designs, with pin counts up to 304 available in the broader MAX 9560 family. Architecturally, the EPM9560RC208-15N uses EEPROM configuration memory to retain the user logic across power cycles, removing the need for an external configuration PROM. Its deterministic timing model simplifies worst-case static timing analysis in safety-critical and industrial control applications. The 5.0-V tolerant I/O is directly compatible with TTL and CMOS logic families widely used in legacy industrial designs, telecom infrastructure, and military/aerospace subsystems. Typical applications for the EPM9560RC208-15N include high-speed address decoding and bus interfacing, glue logic for microprocessor/DSP systems, peripheral controllers in industrial automation, telecom backplane bridging, and legacy ASIC/small-FPGA replacement. The 15 ns speed grade suits designs where predictable sub-20 ns timing closure is required without the complexity and boot time of an FPGA. When designing with this device, confirm that your tool flow targets the legacy MAX+PLUS II or Quartus MAX 9000 device support library; the bitstream is incompatible with newer MAX II/MAX V CPLDs. JTAG programming via the ByteBlasterMV or USB-Blaster download cable is recommended for production programming. Note that the MAX 9000 family is mature/EOL - design for long-life-cycle availability before committing to a new design. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the manufacturer product page alone.
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
The Intel (formerly Altera) EPM9560RC208-16 is a member of the MAX 9000 in-system programmable Complex Programmable Logic Device (CPLD) family, offering 12,000 usable gates, 560 macrocells, and a 16 ns pin-to-pin logic delay in a 208-pin Power Quad Flat Pack (RQFP) package. It is built on a 0.35 µm CMOS EEPROM process and operates from a 5 V supply, providing non-volatile, instant-on configuration that does not require an external boot PROM. The device features 416 user I/O pins, JTAG (IEEE 1149.1) boundary-scan support, and a 117.6 MHz internal fMAX for high-performance glue-logic integration. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks with a central interconnect fabric. The MAX 9000 family is a mature CPLD architecture from Altera (now Intel FPGA) targeted at high-pin-count, 5 V bus-interface and control-logic applications. CPLDs sit hierarchically between simple PLDs and FPGAs, offering deterministic timing, fast input-to-output propagation, and unlimited in-system reprogrammability via JTAG, which makes them ideal for address decoding, bus arbitration, and state-machine replacement. Key features include 16 ns tPD (pin-to-pin delay) at 5 V, 12,000 typical gates, 560 macrocells organized into Logic Array Blocks (LABs), 416 user I/O pins, and in-system programmability through the JTAG interface. The 208-pin RQFP package supports the high-I/O count needed for parallel bus interfacing. Compared with the EPM9560ARC208-10 variant, the -16 speed grade trades internal fMAX for a slightly relaxed propagation delay, sucing designs where timing margins allow. Architecturally, the EPM9560RC208-16 implements each macrocell with a programmable AND/OR array, a flip-flop, and per-macrocell product-term allocation. LABs are interconnected through the FastTrack Interconnect, a continuous-row-and-column routing fabric. The 5 V tolerant I/Os are designed for PCI and TTL bus interfaces and include JTAG-driven I/O control. Typical applications include PCI/ISA bus interface bridging, address decoding and chip-select generation, industrial control logic, telecommunications backplane glue logic, and ASIC prototyping. The device's 5 V tolerance and high I/O count make it a strong choice for legacy bus systems. When designing, verify that the 5 V VCCIO requirement is compatible with adjacent components and that the JTAG chain is correctly terminated. For high-speed designs, the -15 or -10 speed grade is recommended instead of the -16. This page synthesizes distributor pricing, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-16 not collected in the manufacturer datasheet.
EPM9560RC208-17 - MAX 9000 CPLD 12K Gates 560 Macro Cells | Altera
The Altera (Intel) EPM9560RC208-17 is a MAX 9000 family in-system-programmable, high-density, high-performance Erasable Programmable Logic Device (EPLD/CPLD) housed in a 208-pin RQFP package. Built on an advanced CMOS EEPROM technology, this device delivers roughly 12,000 usable gates and 560 macro cells, organized as 16 Logic Array Blocks (LABs) of 40 macro cells each, with a 17 ns pin-to-pin delay and counter speeds reaching approximately 117.6 MHz. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and high-density FPGAs in the programmable logic taxonomy. CPLDs use a classic AND-OR PLA structure with EEPROM or flash configuration memory, providing deterministic timing, instant-on behavior, and high fan-in. They are commonly used for glue logic, address decoding, bus interfacing, and state-machine control. Within Altera's portfolio, the MAX 9000 series is a third-generation MAX architecture family positioned for high-density industrial designs. Key features of the EPM9560RC208-17 include 212 user I/O pins (suitable for bus-intensive designs), a 5V VCC core, in-system programmability via IEEE 1149.1 JTAG, and Altera's classic MAX architecture that supplies deterministic 17 ns tPD with consistent routing delays regardless of logic utilization. The EEPROM cells are rated for at least 100 program/erase cycles, supporting design iteration and field upgrades. From an architectural standpoint, the device contains 16 LABs interconnected via a programmable interconnect array (PIA). Each macro cell includes a programmable AND/OR array feeding a configurable flip-flop, allowing registered or combinatorial outputs. The interconnect uses continuous, fast-channel routing so that delays do not depend on logic density - a key advantage over FPGAs in critical timing paths. Typical applications include 5V industrial glue logic, address decoding for microprocessor and DSP buses, peripheral interfacing in legacy telecom and factory automation systems, pin-compatible replacements for mature designs, and any application requiring predictable 17 ns timing at 5V. Designers often pair the EPM9560RC208-17 with parallel-bus microcontrollers such as the 80C186, 68k, or MIPS-style processors, or use it as a peripheral controller on VME/PCI-derivative buses. When designing with this part, note that the EPM9560RC208-17 is part of the mature MAX 9000 family, originally released in the mid-1990s. Long-term availability varies; engineers should verify current lifecycle status with Intel/Altera before committing to new designs. The 208-pin RQFP package provides ample I/O but consumes significant board area versus modern QFP/BGA packages - plan PCB layout accordingly. This page synthesizes distributor stock, parametric drop-in alternatives, lifecycle indicators, and design notes not found in the manufacturer datasheet, helping engineers evaluate the EPM9560RC208-17 for both legacy maintenance and new 5V designs.
EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
The Altera EPM9560RC208-18 is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 12,000 usable gates and 560 macrocells, delivering a 18 ns pin-to-pin propagation delay in a 208-pin RQFP (Power Quad Flat Pack) package operating from a 5 V supply. It is a mature, EOL-era programmable logic device widely used in legacy industrial, telecom, and military designs. A CPLD (Complex Programmable Logic Device) is a programmable logic IC built from an array of macrocells and a programmable interconnect matrix, sitting between simple PAL/GAL devices and full FPGAs in the programmable logic hierarchy. MAX 9000 devices use EEPROM-based configuration, so they retain their logic configuration without an external configuration PROM, unlike SRAM-based FPGAs. Key features of the EPM9560RC208-18 include 560 macrocells, 12,000 usable gates, up to 149 user I/O pins, 5 V core and I/O operation, and a maximum operating frequency of approximately 117.6 MHz for the -15 speed grade family. The -18 suffix denotes an 18 ns pin-to-pin propagation delay, making it the mid-speed grade of the EPM9560RC208 family. The MAX 9000 architecture uses a CMOS EEPROM process with a global clock network, programmable interconnect array, and per-macrocell flip-flops, giving deterministic timing that is critical for legacy bus-interface and glue-logic replacement designs. Because timing is fixed and non-volatile, the device powers up in a known state within microseconds. Typical applications include legacy industrial control boards, telecom line-card glue logic, military/aerospace retrofit designs, test equipment, and replacement of discrete 74-series logic. The 208-pin RQFP package is form, fit and functionally equivalent to the discontinued 208-pin CQFP package per Altera's product discontinuance notice. When designing with this device, note that it is a mature/EOL part: verify availability, plan for last-time-buy, and consider whether a modern CPLD or small FPGA is a better long-term path. The 5 V I/O is directly compatible with legacy TTL logic, which is a key reason the part remains in demand. This page synthesizes distributor availability, drop-in speed-grade alternatives, and practical design notes for the EPM9560RC208-18 that are not consolidated in the manufacturer datasheet.
EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera
The Altera EPM9560RC208-19 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, featuring 560 macrocells, 12,000 usable gates, and a pin-to-pin propagation delay of 19 ns, housed in a 208-pin RQFP package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device provides 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, enabling boundary-scan test, in-system configuration, and rapid prototyping without external programmers. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell fabric and deterministic timing. Within the broader programmable logic hierarchy, CPLDs sit below FPGAs in density but above simple PLDs in logic capacity, offering instant-on behavior, single-chip solutions, and predictable routing delays that make them ideal for glue logic, bus interface, and state-machine replacement roles. Key features of the EPM9560RC208-19 include 772 flip-flops, 149 user I/O pins, 5-V tolerant I/O with multi-voltage interface support, JTAG-compliant ISP, and a maximum toggle frequency that supports high-speed control logic. The 208-pin RQFP (also called PQFP) package provides a generous I/O count for system integration while retaining a manageable footprint for production assembly. The -19 speed grade designates the 19 ns propagation delay bin. Technical depth: the MAX 9000 architecture uses a programmable interconnect array (PIA) that routes signals between Logic Array Blocks (LABs), giving every signal a consistent and predictable delay regardless of placement. This deterministic timing eliminates the place-and-route iterations often required by FPGAs. The EEPROM-based configuration cell is non-volatile, so the device powers up instantly in its programmed state with no external boot memory required. Typical applications include bus interfacing (PCI, ISA, VME), state-machine replacement, address decoding and glue logic in microprocessor systems, peripheral control, and high-volume glue-logic consolidation. The wide I/O count makes it particularly suited to 32-bit and 64-bit system bus bridging tasks. Design consideration: when migrating a MAX 9000 design to a newer family, verify that the pinout and JTAG programming flow are compatible. The RQFP-208 footprint differs from later BGA-packaged MAX II/MAX V devices, so PCB redesign is generally required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing engineers with a single reference for the EPM9560RC208-19 across sourcing, design, and lifecycle decisions.
EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel
The Intel (Altera) EPM9560RC208-20 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (Power Quad Flat Pack) surface-mount package. It operates from a 5.0 V supply with in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic array blocks and macrocells into a single non-volatile device, allowing designers to implement custom digital logic without fabricating an ASIC. Within the programmable logic hierarchy, a CPLD sits between simple PLDs and FPGAs: it offers lower density than an FPGA but provides deterministic, non-volatile, single-chip operation with predictable timing. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using CMOS EEPROM technology. Key features of the EPM9560RC208-20 include 560 macrocells organized into 35 logic array blocks, 153 user I/O pins, 12,000 gates of logic capacity, and a 20 ns pin-to-pin delay that supports system clock rates up to 100 MHz. The EEPROM-based configuration is retained without external configuration memory, eliminating the boot-time configuration step required by SRAM-based FPGAs. The MAX 9000 architecture uses a continuous interconnect scheme that delivers uniform, predictable propagation delays independent of routing, which simplifies static timing analysis. The 5.0 V core and I/O operation provides direct TTL/CMOS compatibility for legacy 5 V systems, and the built-in JTAG boundary-scan interface supports both in-system programming and board-level test. Typical applications include glue logic for legacy 5 V microprocessor buses, PCI and ISA interface bridging, industrial control state machines, and replacement of discrete 74-series logic in existing designs. The 208-pin RQFP package is form, fit, and functionally equivalent to the discontinued 208-pin CQFP version, per Altera's product discontinuance notice. When designing with this device, note that the MAX 9000 family is a mature, legacy product line; verify current availability and consider migration to a modern CPLD or small FPGA for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC208-20C - MAX 9000 CPLD 560 Macro Cells | Altera
The Altera EPM9560RC208-20C is a MAX 9000 family EEPROM-based complex programmable logic device (CPLD) with 560 macrocells, 12,000 usable gates, 772 flip-flops, and 149 user I/O pins, delivering a 20 ns pin-to-pin propagation delay in a 208-pin RQFP (Power Quad Flat Pack) package operating from a 5.0 V supply. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and macrocells with a non-volatile EEPROM configuration memory, allowing the device to retain its logic configuration without an external configuration PROM. Within the programmable logic hierarchy, the CPLD sits between simple PLDs (PAL/GAL) and FPGAs: CPLDs offer deterministic, pin-to-pin timing and instant-on operation, while FPGAs provide higher logic density at the cost of external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture and supports 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. Key differentiators of the EPM9560RC208-20C include its 560 macrocells (the highest density in the MAX 9000 family), 149 configurable I/O lines, 12,000 usable gates, and 20 ns commercial-grade propagation delay. The EEPROM configuration cell provides non-volatile, instant-on operation, eliminating the configuration PROM required by SRAM-based FPGAs and improving system security against configuration readback. The device uses CMOS EEPROM technology with 5.0 V core and I/O operation, and is offered in a 208-pin RQFP package (JESD-30 code S-PQFP-G208) with gull-wing terminals. The MAX 9000 architecture routes signals through a programmable interconnect array (PIA) that provides predictable, fixed delays between logic array blocks, enabling worst-case timing analysis without post-fit simulation. Typical applications include glue logic consolidation in industrial control boards, bus interface and address decoding in legacy 5 V microprocessor systems, state machines for instrumentation, and prototyping of moderate-complexity digital logic where instant-on operation and 5 V compatibility are required. When designing with the EPM9560RC208-20C, note that the device is a legacy 5 V CPLD; verify availability of the MAX+PLUS II development toolchain and confirm the target board provides a clean 5.0 V rail with adequate decoupling on every VCC pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC208-20N - MAX 9000 CPLD 560 Macrocell 20ns | Intel
The Intel (Altera) EPM9560RC208-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 560 macrocells, 12,000 usable gates, and a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad/plastic quad flat pack) package. It is a 5.0 V EEPROM-based programmable logic device with in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural flexibility of a small FPGA with the non-volatile, instant-on behavior of a PAL/GAL. In the product hierarchy, the MAX 9000 sits above simple PLDs and below FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. Because configuration is stored in EEPROM cells rather than SRAM, the EPM9560RC208-20N is live at power-up with no external configuration memory, a decisive advantage in glue-logic, bus-bridging, and power-up sequencing roles. Key differentiators of the MAX 9000 architecture include its Multiple Array MatriX (MAX) structure with 560 macrocells organized into logic array blocks, 12,000 usable gates, and 208-pin RQFP packaging that exposes up to 149 user I/O pins. The -20 speed grade guarantees a 20 ns pin-to-pin tPD, while the -20N suffix denotes the lead-free (RoHS-compatible) package variant. The device supports 5.0 V in-system programming via JTAG, allowing field reconfiguration without removing the part from the board. Architecturally, the MAX 9000 family uses third-generation CMOS EEPROM technology with a programmable interconnect array that routes signals between logic array blocks. Each macrocell contains a flip-flop and product-term logic, enabling registered or combinatorial operation. The 20 ns propagation delay supports system clock rates in the tens of MHz for combinatorial paths, and the 5.0 V I/O is directly compatible with legacy TTL and 5 V CMOS logic families. Typical applications include bus interface and protocol bridging, address decoding and chip-select generation, power-up sequencing and reset control, legacy system glue logic, and industrial control backplanes. The instant-on EEPROM configuration makes it especially suited to systems that cannot tolerate FPGA configuration latency. A key design consideration is that the MAX 9000 family is a mature, legacy 5.0 V technology; new designs should evaluate modern low-voltage CPLDs, but for maintenance and drop-in replacement of existing boards the EPM9560RC208-20N remains the reference part. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
The Intel (formerly Altera) EPM9560RC208-21 is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin Power Quad Flat Pack (RQFP/RQ208) package. The device features 560 macrocells, 772 flip-flops, and 149 user I/O pins, with a maximum propagation delay of 21 ns as indicated by the -21 speed grade suffix. It operates from a 5.0 V core supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that combines the architecture of multiple PAL/GAL-like logic blocks interconnected via a programmable switch matrix. CPLDs are positioned between simple SPLDs and FPGAs in the programmable logic hierarchy, offering predictable timing, instant-on behavior (because configuration is stored in EEPROM), and high pin counts for glue-logic, bus-interface, and state-machine applications. The MAX 9000 family represents Altera's third-generation Multiple Array MatriX architecture and was one of the highest-density CPLD families ever shipped. Key features of the EPM9560RC208-21 include 12,000 usable gates, 16 Logic Array Blocks (LABs), an enhanced interconnect switch matrix, and CMOS EEPROM-based configuration memory that eliminates the need for a separate boot PROM. Per-pin slew-rate control and a programmable security bit for design protection are standard. The 208-pin RQFP package provides ample I/O for parallel bus interfaces, backplane drivers, and ASIC prototyping. Typical applications span telecommunication line cards, industrial control and instrumentation, ASIC prototyping, bus decoding and address mapping, peripheral glue logic in microprocessor/microcontroller systems, and legacy designs where 5 V tolerance is required. The 21 ns propagation delay supports bus interfaces up to ~33 MHz, while the high I/O count accommodates wide data buses. When laying out the EPM9560RC208-21, observe the standard PQFP land pattern recommendations, provide at least four dedicated GND and VCC pins with low-impedance decoupling, and ensure the JTAG chain order matches the BSDL file. The part is mature: production is in last-time-buy phase, and the Altera Product Discontinuance Notice specifies that RQFP-package EPM9560 devices are form, fit, and functionally equivalent to the older CQFP package that was discontinued first. This datasheet synthesizes device characteristics from the MAX 9000 family datasheet and PN-21 device ordering information.
EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera
The Intel / Altera EPM9560RC208-3 is a high-density MAX 9000 family Erasable Programmable Logic Device (EPLD) delivering 560 macrocells and 12,000 usable gates in a 208-pin Power Quad Flat Pack (RQFP) package. Built on a 0.5 µm CMOS EPROM process, it integrates multiple Logic Array Blocks (LABs) with a Programmable Interconnect Array (PIA), providing designers with the largest device in the classic Altera MAX 9000 family for glue-logic, bus-interface, and state-machine integration. A programmable logic device such as an EPLD is a non-volatile, in-system re-programmable integrated circuit that replaces dozens of discrete TTL/CMOS glue-logic ICs. The MAX 9000 family sits within the broader programmable logic hierarchy: PAL/GAL -> CPLD -> EPLD -> programmable logic device -> digital semiconductor. Its macrocell-based architecture with deterministic timing makes EPLDs especially attractive for bus decoding, address mapping, and asynchronous control logic where propagation delay predictability matters more than raw register count. Key features include 560 macrocells, 16 Logic Array Blocks (LABs), a maximum operating frequency of [DATA_NEEDED: f_MAX], a pin-to-pin delay of approximately 3 ns (speed grade -3, the slowest of the -3/-10/-12/-15/-17/-20 series), and 5V tolerant I/O. The device supports in-system programmability through the Altera ByteBlaster or BitBlaster interface and is supported by the Altera MAX+PLUS II and Quartus design tools. Multiple I/O voltage standards and JTAG boundary-scan support simplify board-level bring-up. Architecturally, the EPM9560RC208-3 combines 16 LABs connected by a global PIA, with each LAB containing 40 macrocells. Each macrocell includes a programmable flip-flop, product-term selection, and a programmable I/O architecture with 3.3V or 5V interfaces. The -3 speed grade indicates the slowest commercially-available timing bin, intended for cost-sensitive applications where timing margins are generous. Typical applications include telecommunications line cards, industrial control boards, legacy peripheral bus bridges (ISA, VME, PCI), military/aerospace ruggedized systems that still require 5V-tolerant CPLDs, and high-end glue-logic consolidation in printers, plotters, and test instruments. Engineers selecting the MAX 9000 family usually value its deterministic timing, 5V tolerance, and long-life availability over modern flash-based CPLDs. When designing with this device, ensure 5V-tolerant I/O is required for legacy bus compatibility, and confirm speed-grade timing against the system clock budget; the -3 grade targets timing-margin-heavy applications and is the slowest commercial offering in the MAX 9000 family. This page synthesizes distributor pricing, drop-in same-package alternatives (EPM9560RC208-10, EPM9560RC208-15, EPM9560RC208-20 from the same family), lifecycle observations, and practical design notes not found in a single manufacturer datasheet.