2ED2103S06FXUMA1 vs 2ED21064S06JXUMA1 Comparison
Detailed side-by-side comparison of 2ED2103S06FXUMA1 by Infineon and 2ED21064S06JXUMA1 by Infineon. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Infineon
2ED21064S06JXUMA1
2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21064S06JXUMA1 β ActiveSpecification Comparison
| Parameter | 2ED2103S06FXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Brand | Infineon | Infineon |
| Category | Power MOSFET Drivers | Power MOSFET Drivers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.94 | $0.85 |
| Function | Half-Bridge Gate Driver | High-Side and Low-Side Gate Driver |
| Configuration | Non-Inverting | Half-Bridge (2 outputs, non-inverting) |
| Technology | High-Voltage Level Shift (SOI) | β |
| Number of Drivers | 2 (high-side + low-side) | β |
| Driven Device Type | IGBT, N-Channel MOSFET | β |
| High-Side Offset Voltage (Max) | 650 V | β |
| Bootstrap Voltage (Max) | 675 V | β |
| Supply Voltage (VCC) | 10 V to 20 V | 10 V to 20 V |
| Source Current (typ.) | 0.29 A | β |
| Sink Current (typ.) | 0.7 A | β |
| Bootstrap Diode | Integrated | Integrated |
| Logic Input Compatibility | 3.3 V / 5 V | β |
| Under-Voltage Lockout (UVLO) | Yes (VCC and VBS) | β |
| Package | PG-DSO-8-69 (DSO-8 with exposed pad) | PG-DSO-14 (14-pin SOIC) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | -40C to +125C | β |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| RoHS Status | Compliant | ROHS3 Compliant |
| Topology | β | High-Side, Low-Side with integrated bootstrap diode |
| Maximum Offset / Boot Voltage | β | 650 V |
| Source Current (typical) | β | 0.29 A |
| Sink Current (typical) | β | 0.7 A |
| Rise Time (typical) | β | [DATA_NEEDED: rise time] |
| Fall Time (typical) | β | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | β | 100 ns |
| Channel-to-Channel Delay Match | β | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | β | Yes (both channels) |
| Input Logic Compatibility | β | 3.3 V / 5 V CMOS |
| Operating Temperature | β | -40C to +125C |
| Negative Gate Drive Robustness | β | -0.7 V |