2ED2103S06FXUMA1 vs 2ED21064S06JXUMA1 Comparaison
Comparaison détaillée côte à côte de 2ED2103S06FXUMA1 par Infineon et 2ED21064S06JXUMA1 par Infineon. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | 2ED2103S06FXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Marque | Infineon | Infineon |
| Catégorie | Power MOSFET Drivers | Power MOSFET Drivers |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,94 | $0,85 |
| Fonction | Half-Bridge Gate Driver | High-Side and Low-Side Gate Driver |
| Configuration | Non-Inverting | Half-Bridge (2 outputs, non-inverting) |
| Technology | High-Voltage Level Shift (SOI) | — |
| Number of Drivers | 2 (high-side + low-side) | — |
| Driven Device Type | IGBT, N-Channel MOSFET | — |
| High-Side Offset Voltage (Max) | 650 V | — |
| Bootstrap Voltage (Max) | 675 V | — |
| Supply Voltage (VCC) | 10 V to 20 V | 10 V to 20 V |
| Source Current (typ.) | 0.29 A | — |
| Sink Current (typ.) | 0.7 A | — |
| Bootstrap Diode | Integrated | Integrated |
| Logic Input Compatibility | 3.3 V / 5 V | — |
| Under-Voltage Lockout (UVLO) | Yes (VCC and VBS) | — |
| Boîtier | PG-DSO-8-69 (DSO-8 with exposed pad) | PG-DSO-14 (14-pin SOIC) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | -40C to +125C | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Statut RoHS | Compliant | ROHS3 Compliant |
| Topologie | — | High-Side, Low-Side with integrated bootstrap diode |
| Maximum Offset / Boot Voltage | — | 650 V |
| Source Current (typical) | — | 0.29 A |
| Sink Current (typical) | — | 0.7 A |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | — | 100 ns |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Température de fonctionnement | — | -40C to +125C |
| Negative Gate Drive Robustness | — | -0.7 V |