2ED2103S06FXUMA1 vs 2ED21064S06JXUMA1 Comparación
Comparación detallada lado a lado de 2ED2103S06FXUMA1 por Infineon y 2ED21064S06JXUMA1 por Infineon. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Infineon
2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon
2ED21064S06JXUMA1 ✓ ActivoComparación de especificaciones
| Parámetro | 2ED2103S06FXUMA1 | 2ED21064S06JXUMA1 |
|---|---|---|
| Marca | Infineon | Infineon |
| Categoría | Power MOSFET Drivers | Power MOSFET Drivers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,94 | $0,85 |
| Función | Half-Bridge Gate Driver | High-Side and Low-Side Gate Driver |
| Configuration | Non-Inverting | Half-Bridge (2 outputs, non-inverting) |
| Technology | High-Voltage Level Shift (SOI) | — |
| Number of Drivers | 2 (high-side + low-side) | — |
| Driven Device Type | IGBT, N-Channel MOSFET | — |
| High-Side Offset Voltage (Max) | 650 V | — |
| Bootstrap Voltage (Max) | 675 V | — |
| Supply Voltage (VCC) | 10 V to 20 V | 10 V to 20 V |
| Source Current (typ.) | 0.29 A | — |
| Sink Current (typ.) | 0.7 A | — |
| Bootstrap Diode | Integrated | Integrated |
| Logic Input Compatibility | 3.3 V / 5 V | — |
| Under-Voltage Lockout (UVLO) | Yes (VCC and VBS) | — |
| Encapsulado | PG-DSO-8-69 (DSO-8 with exposed pad) | PG-DSO-14 (14-pin SOIC) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | -40C to +125C | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Estado RoHS | Compliant | ROHS3 Compliant |
| Topología | — | High-Side, Low-Side with integrated bootstrap diode |
| Maximum Offset / Boot Voltage | — | 650 V |
| Source Current (typical) | — | 0.29 A |
| Sink Current (typical) | — | 0.7 A |
| Rise Time (typical) | — | [DATA_NEEDED: rise time] |
| Fall Time (typical) | — | [DATA_NEEDED: fall time] |
| Propagation Delay (typical) | — | 100 ns |
| Channel-to-Channel Delay Match | — | [DATA_NEEDED: channel-to-channel delay match] |
| Under-Voltage Lockout | — | Yes (both channels) |
| Input Logic Compatibility | — | 3.3 V / 5 V CMOS |
| Temperatura de funcionamiento | — | -40C to +125C |
| Negative Gate Drive Robustness | — | -0.7 V |