EP1M350F780I5 vs EP1M350F780C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1M350F780I5 sa pamamagitan ng Altera at EP1M350F780C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndPagsanggunian na paghahambing
| Parametro | EP1M350F780I5 | EP1M350F780C8 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | Altera Mercury (EP1M) Enhanced Configuration Device | Altera APEX Mercury (EP1M) |
| Fungsi | FPGA configuration PROM with integrated controller | — |
| Storage Density Code | 350 (high-density) | — |
| Supported Configuration Schemes | Passive Serial, Active Serial, Fast Passive Parallel | — |
| Internal Architecture | Configuration controller + flash memory array | — |
| Programming Method | In-system programmable via Altera Quartus / JTAG | — |
| Packhaging | 780-ball FineLine BGA (F780) | 780-ball FineLine BGA |
| Temperature Grade (suffix "I") | Industrial | — |
| Speed Grade | 5 | C8 (commercial, speed bin 8) |
| Target FPGA Compatibility | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Cascade / Multi-FPGA Support | Yes, supports daisy-chained multi-FPGA boot | — |
| Read-Back | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown (legacy device) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Typical Gates | — | 350,000 |
| Maximum Logic Elements (LEs) | — | 12,160 |
| Embedded RAM Blocks | — | 4 dual-port RAM blocks |
| Temperature na Operasyon | — | 0C to +85C (commercial) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, LVDS (up to 20 standards) |
| Global Clock Networks | — | 8 |
| Configuration Interface | — | IEEE 1532 / passive serial / JTAG |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |
| In-System Programmability | — | Yes (ISP via JTAG) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |