EP910DM883B vs EP910DC-35 Comparison

Detailed side-by-side comparison of EP910DM883B by Altera and EP910DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910DM883B EP910DC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Manufacturer Altera (now part of Intel) —
Family Classic EPLD - EP910 Series Classic EPLD EP910
Device Type Erasable Programmable Logic Device (EPLD) UV-Erasable CMOS PLD (PAL-type)
Architecture PAL-type AND-OR-NOT, CMOS PAL-type sum-of-products AND-OR array
Macrocells 24 24
Inputs 36 —
Outputs 24 —
Product Terms 240 240
Propagation Delay (tPD) 40 ns (typical) —
Maximum Clock Frequency 25 MHz 37 MHz (typical, internal)
Supply Voltage (VCC) 5 V —
Programming Voltage (VPP) 12.5 V (UV-erase window) —
Operating Temperature -55 °C to +125 °C (military) 0 °C to +70 °C (commercial)
Package CDIP-40 (Ceramic DIP, 40-pin) 40-pin CDIP (Ceramic DIP) with quartz window
Mounting Type Through-Hole (DIP) —
MIL Processing MIL-STD-883B Class B —
Configuration Memory UV-erasable EPROM —
Logic Elements Combinational + Registered —
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 900 gates
Dedicated Inputs — 12
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

Datasheets & Resources

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