EP910DM883B vs EP910DC-35 Comparación
Comparación detallada lado a lado de EP910DM883B por Altera y EP910DC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DM883B | EP910DC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,10 | $10,95 |
| Manufacturer | Altera (now part of Intel) | — |
| Family | Classic EPLD - EP910 Series | Classic EPLD EP910 |
| Device Type | Erasable Programmable Logic Device (EPLD) | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | PAL-type AND-OR-NOT, CMOS | PAL-type sum-of-products AND-OR array |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns (typical) | — |
| Frecuencia de reloj máxima | 25 MHz | 37 MHz (typical, internal) |
| Supply Voltage (VCC) | 5 V | — |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Temperatura de funcionamiento | -55 °C to +125 °C (military) | 0 °C to +70 °C (commercial) |
| Encapsulado | CDIP-40 (Ceramic DIP, 40-pin) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Tipo de montaje | Through-Hole (DIP) | — |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Usable Gates | — | 900 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |