EP910DM883B vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM883B sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DM883B EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Altera (now part of Intel) —
Family Classic EPLD - EP910 Series Classic EPLD EP910
Device Type Erasable Programmable Logic Device (EPLD) UV-Erasable CMOS PLD (PAL-type)
Architecture PAL-type AND-OR-NOT, CMOS PAL-type sum-of-products AND-OR array
Macrocells 24 24
Inputs 36 —
Outputs 24 —
Product Terms 240 240
Propagation Delay (tPD) 40 ns (typical) —
Maksimum na Taktiko ng Oras 25 MHz 37 MHz (typical, internal)
Supply Voltage (VCC) 5 V —
Programming Voltage (VPP) 12.5 V (UV-erase window) —
Temperature na Operasyon -55 °C to +125 °C (military) 0 °C to +70 °C (commercial)
Packhaging CDIP-40 (Ceramic DIP, 40-pin) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole (DIP) —
MIL Processing MIL-STD-883B Class B —
Configuration Memory UV-erasable EPROM —
Logic Elements Combinational + Registered —
Tindminan RoHS [DATA_NEEDED: RoHS status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 900 gates
Dedicated Inputs — 12
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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