EPC1LC20-WCEC52 vs EPC1L20 比較
詳細並排比較 EPC1LC20-WCEC52 由 Altera 與 EPC1L20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1LC20-WCEC52 | EPC1L20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | 啟用中 |
| 記憶體類型 | OTP Configuration PROM (Anti-fuse) | OTP Configuration PROM (Flash) |
| 記憶體容量 | 1 Mbit (1,048,576 bits) | 1 Mbit |
| 組織 | 212,942 x 1 bit | — |
| 介面 | Serial (Altera FPP/PS configuration protocol) | Serial / FPP configuration + JTAG (IEEE 1149.1) |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Supply Voltage (VCC) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V (FPGA interface) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Programmability | One-Time Programmable (OTP) | One-Time Programmable (OTP) |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 20-pin PLCC (J-lead, through-hole, 9x9 mm) | 20-pin PLCC (9x9 mm) |
| Package Mounting | Through-hole (also accepts PLCC socket) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, MAX series | — |
| Programming Interface | JTAG (IEEE Std 1149.1) ISP | — |
| 腳位數 | 20 | — |
| 生命週期狀態 | Obsolete (recommended replacement: EPCQ family or newer serial config devices) | — |
| Configuration Clock (max) | — | 8 MHz |
| Flash Access Time | — | 90 ns (approx.) |
| Max Read Bandwidth | — | 160 Mbps (16-bit DQ bus) |
| 供應電壓 | — | 3.3 V (typical) |
| 安裝類型 | — | Through-Hole / Socket |
| JTAG / ISP Support | — | Yes (IEEE 1149.1) |
| Compatible FPGA Series | — | Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families |