EPC2L120 vs EPC2L120N 比較
詳細並排比較 EPC2L120 由 Altera 與 EPC2L120N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2L120 | EPC2L120N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| 記憶體類型 | Configuration PROM (Flash-based) | — |
| Density | 120 Kbit | — |
| Configuration Interface | Serial, FPGA-targeted | — |
| Operating Voltage | 2.7 V to 3.6 V (3.3 V typ) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| 封裝 | PLCC-20 | 84-pin PLCC (J-Lead) |
| Compatible FPGAs | Altera Cyclone, Cyclone II, APEX-series | — |
| 工作溫度 | -40 C to +85 C | [DATA_NEEDED: industrial temp range] |
| CONF_DONE Output | Open-drain, wire-OR capable | — |
| Data Retention | 20 years (per Altera datasheet family) | — |
| Program/Erase Cycles | 100 cycles minimum | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | unknown | unknown |
| Lead-Free | unknown | — |
| Family | EPC2 (Enhanced Configuration) | EPC2 (Enhanced Configuration Device) |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |