EPC2L120 vs EPC2L120N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L120 sa pamamagitan ng Altera at EPC2L120N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2L120 EPC2L120N
Brand Altera Intel
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Uri ng Memory Configuration PROM (Flash-based) —
Density 120 Kbit —
Configuration Interface Serial, FPGA-targeted —
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Packhaging PLCC-20 84-pin PLCC (J-Lead)
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series —
Temperature na Operasyon -40 C to +85 C [DATA_NEEDED: industrial temp range]
CONF_DONE Output Open-drain, wire-OR capable —
Data Retention 20 years (per Altera datasheet family) —
Program/Erase Cycles 100 cycles minimum —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS unknown unknown
Lead-Free unknown —
Family EPC2 (Enhanced Configuration) EPC2 (Enhanced Configuration Device)
Device Type — Configuration Device for SRAM-based LUT FPGAs
Manufacturer — Intel (formerly Altera)
Memory Capacity — 165,888 bits (400,000 gates equivalent)
Operating Voltage (VCCIO) — 2.7 V to 3.6 V
5V Tolerance — Yes (5V-tolerant I/O)
Configuration Clock (FPP) — Up to 66 MHz
Configuration Clock (PS) — Up to 33 MHz
Internal Oscillator — 8 MHz with programmable divider
JTAG Interface — IEEE Std 1149.1 compliant, ISP support
Programming Cycles — 100,000 erase/program cycles
Sector Erase Time — [DATA_NEEDED: typical sector erase time]
Configuration Schemes — FPP, PS, JTAG, daisy chain
Supported FPGA Families — Cyclone, APEX, FLEX, Mercury, ACEX, Stratix

Mga Datasheets at Resources

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