EPM240T100I5 vs EPM240T100I3N Comparison
Detailed side-by-side comparison of EPM240T100I5 by Intel and EPM240T100I3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N β Last Time BuySpecification Comparison
| Parameter | EPM240T100I5 | EPM240T100I3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.88 | $5.45 |
| Family | MAX II | MAX II |
| Series | EPM240 | β |
| Device Sub-family | EPM240T100 | β |
| Logic Elements (LE) | 240 | β |
| Equivalent Macrocells | 192 | β |
| User Flash Memory (UFM) | 8 Kbits | β |
| Maximum User I/O Pins | 80 | 80 |
| Package | TQFP-100 (100-pin) | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Operating Temperature | -40C to +100C (industrial) | β |
| Speed Grade | I5 | 3 |
| Core Voltage | 3.3 V | β |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Propagation Delay (typical) | 4-7 ns | β |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 ISP |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant |
| Device Logic Elements / Macrocells | β | 192 macrocells |
| Number of Logic Array Blocks (LABs) | β | 4 |
| On-chip User Flash Memory | β | 8 Kbits |
| Internal Performance | β | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | β | 4.6 ns |
| Global Clock Networks | β | 4 |
| Technology Node | β | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | β | 2.5 V / 3.3 V |
| Operating Junction Temperature | β | -40C to +100C (industrial, 'I' grade) |
| Instant-on (non-volatile) | β | Yes (flash-based) |
| MSL Level | β | 3 (per JEDEC J-STD-020) |