EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
MPN: EPM240T100I3N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $8.1 | $81.00 |
| 100 | $7.05 | $705.00 |
| 500 | $6.2 | $3,100.00 |
| 1,000 | $5.45 | $5,450.00 |
Drop-in alternatives for EPM240T100I3N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM240T100I3N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device Logic Elements / Macrocells | 192 macrocells |
| Maximum User I/O Pins | 80 |
| Number of Logic Array Blocks (LABs) | 4 |
| On-chip User Flash Memory | 8 Kbits |
| Internal Performance | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | 4.6 ns |
| Global Clock Networks | 4 |
| Technology Node | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | 2.5 V / 3.3 V |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Junction Temperature | -40C to +100C (industrial, 'I' grade) |
| Speed Grade | 3 |
| Package | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Programming Interface | JTAG / IEEE 1149.1 ISP |
| Instant-on (non-volatile) | Yes (flash-based) |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
EPM240T100I3N Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | I/O — User I/O (bank 1) |
| Pin 3 | I/O — User I/O (bank 1) |
| Pin 4 | I/O — User I/O (bank 1) |
| Pin 5 | I/O — User I/O (bank 1) |
| Pin 6 | I/O — User I/O (bank 1) |
| Pin 7 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 8 | I/O — User I/O (bank 1) |
| Pin 9 | I/O — User I/O (bank 1) |
| Pin 10 | I/O — User I/O (bank 1) |
| Pin 11 | I/O — User I/O (bank 1) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — User I/O (bank 1) |
| Pin 14 | I/O — User I/O (bank 1) |
| Pin 15 | I/O — User I/O (bank 1) |
| Pin 16 | I/O — User I/O (bank 1) |
| Pin 17 | I/O — User I/O (bank 1) |
| Pin 18 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 19 | I/O — User I/O (bank 1) |
| Pin 20 | I/O — User I/O (bank 1) |
| Pin 21 | I/O — User I/O (bank 1) |
| Pin 22 | I/O — User I/O (bank 1) |
| Pin 23 | GND — Ground |
| Pin 24 | I/O — User I/O (bank 2) |
| Pin 25 | I/O — User I/O (bank 2) |
| Pin 26 | I/O — User I/O (bank 2) |
| Pin 27 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 28 | I/O — User I/O (bank 2) |
| Pin 29 | I/O — User I/O (bank 2) |
| Pin 30 | I/O — User I/O (bank 2) |
| Pin 31 | I/O — User I/O (bank 2) |
| Pin 32 | GND — Ground |
| Pin 33 | I/O — User I/O (bank 2) |
| Pin 34 | I/O — User I/O (bank 2) |
| Pin 35 | I/O — User I/O (bank 2) |
| Pin 36 | I/O — User I/O (bank 2) |
| Pin 37 | I/O — User I/O (bank 2) |
| Pin 38 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 39 | I/O — User I/O (bank 2) |
| Pin 40 | I/O — User I/O (bank 2) |
| Pin 41 | I/O — User I/O (bank 2) |
| Pin 42 | I/O — User I/O (bank 2) |
| Pin 43 | GND — Ground |
| Pin 44 | I/O — User I/O (bank 3) |
| Pin 45 | I/O — User I/O (bank 3) |
| Pin 46 | I/O — User I/O (bank 3) |
| Pin 47 | I/O — User I/O (bank 3) |
| Pin 48 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 49 | I/O — User I/O (bank 3) |
| Pin 50 | I/O — User I/O (bank 3) |
| Pin 51 | I/O — User I/O (bank 3) |
| Pin 52 | I/O — User I/O (bank 3) |
| Pin 53 | GND — Ground |
| Pin 54 | I/O — User I/O (bank 3) |
| Pin 55 | I/O — User I/O (bank 3) |
| Pin 56 | I/O — User I/O (bank 3) |
| Pin 57 | I/O — User I/O (bank 3) |
| Pin 58 | I/O — User I/O (bank 3) |
| Pin 59 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 60 | I/O — User I/O (bank 3) |
| Pin 61 | I/O — User I/O (bank 3) |
| Pin 62 | I/O — User I/O (bank 3) |
| Pin 63 | I/O — User I/O (bank 3) |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — User I/O (bank 4) |
| Pin 66 | I/O — User I/O (bank 4) |
| Pin 67 | I/O — User I/O (bank 4) |
| Pin 68 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 69 | I/O — User I/O (bank 4) |
| Pin 70 | I/O — User I/O (bank 4) |
| Pin 71 | I/O — User I/O (bank 4) |
| Pin 72 | I/O — User I/O (bank 4) |
| Pin 73 | GND — Ground |
| Pin 74 | I/O — User I/O (bank 4) |
| Pin 75 | I/O — User I/O (bank 4) |
| Pin 76 | I/O — User I/O (bank 4) |
| Pin 77 | I/O — User I/O (bank 4) |
| Pin 78 | I/O — User I/O (bank 4) |
| Pin 79 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 80 | I/O — User I/O (bank 4) |
| Pin 81 | I/O — User I/O (bank 4) |
| Pin 82 | I/O — User I/O (bank 4) |
| Pin 83 | I/O — User I/O (bank 4) |
| Pin 84 | TMS — JTAG Test Mode Select |
| Pin 85 | VCCINT — Core supply voltage (2.5 V or 3.3 V) |
| Pin 86 | TCK — JTAG Test Clock |
| Pin 87 | I/O — User I/O (bank 4 / JTAG bank) |
| Pin 88 | I/O — User I/O (bank 4) |
| Pin 89 | TDO — JTAG Test Data Out |
| Pin 90 | GND — Ground |
| Pin 91 | I/O — User I/O (bank 4) |
| Pin 92 | I/O — User I/O (bank 4) |
| Pin 93 | I/O — User I/O (bank 4) |
| Pin 94 | TDI — JTAG Test Data In |
| Pin 95 | VCCINT — Core supply voltage |
| Pin 96 | I/O — User I/O (bank 4) |
| Pin 97 | I/O — User I/O (bank 4) |
| Pin 98 | I/O — User I/O (bank 4) |
| Pin 99 | I/O — User I/O (bank 4) |
| Pin 100 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM240T100I3N is suitable for 6 applications: Industrial I/O Expansion and Voltage Level Translation, FPGA Configuration and Power-Sequencing Glue Logic, Bus Bridging (I2C/SPI/UART to Parallel GPIO), LED Driver and Lighting State-Machine Controllers, Motor Control Peripheral Interface, Test and Measurement Instrument Front-Ends.
Industrial I/O Expansion and Voltage Level Translation
The EPM240T100I3N's 80 MultiVolt I/O pins and 1.5/1.8/2.5/3.3 V bank support make it ideal for expanding GPIOs or bridging mismatched voltage domains in industrial PLC backplanes. With 4.6 ns tPD1 and deterministic timing, the device delivers glitch-free level shifting between 3.3 V host MCUs and 1.8 V FPGAs without external buffers. Its industrial -40C to +100C junction range survives factory-floor thermal stress, and the 8 Kbit on-chip flash stores board IDs and calibration constants, eliminating a separate EEPROM. Compared to discrete 74LVC buffers, this CPLD reduces board area by 60% and improves design flexibility via JTAG re-programmability. Recommended for: PLCs, industrial sensor hubs, factory-automation modules.
Recommended
FPGA Configuration and Power-Sequencing Glue Logic
The EPM240T100I3N is widely used as a companion CPLD to large FPGAs to handle power sequencing, DONE-pin monitoring, JTAG fan-out, and partial reconfiguration triggers. Its instant-on flash-based design wakes up in microseconds and releases the FPGA's nCONFIG/nCE pins in deterministic order, eliminating FPGA boot-failure risk in mission-critical systems. With 192 macrocells and 80 I/O, the EPM240 can implement complex state machines for multi-rail sequencing (e.g., 1.0 V VCCINT then 1.8 V VTT then 3.3 V I/O), each rail monitored by an analog comparator input. The 100-pin TQFP package allows it to sit adjacent to the FPGA on the same PCB layer. Recommended for: data-center accelerator cards, 5G baseband boards, high-end FPGA development kits.
Recommended
Bus Bridging (I2C/SPI/UART to Parallel GPIO)
The EPM240T100I3N's combination of 192 macrocells and 80 user I/O enables serial-to-parallel bus bridges that fan out a low-pin-count MCU I2C or SPI port into 16, 24, or 32 GPIO lines. Engineers implement address-decoding state machines in the LABs, with 4.6 ns tPD1 latency keeping bus turn-around times below 100 ns even at 1 MHz I2C Fast-mode. The on-chip flash holds I2C device address maps that can be reconfigured via JTAG for board-revision changes, ideal for prototype-to-production transitions. The industrial temperature range supports outdoor and automotive-in-cabin deployments. Recommended for: legacy MCU replacements, sensor hubs, test fixtures.
Recommended
LED Driver and Lighting State-Machine Controllers
Architectural and stage-lighting controllers use the EPM240T100I3N to generate DMX-512, SPI, or PWM outputs that drive chains of WS2812B or APA102 LED pixels. The 4 LABs each contain 16 macrocells and 16 associated DFFs, which the design can partition into independent PWM generators with 16-bit resolution at 1 kHz refresh - more than enough for 256 dim levels per channel. The 80 I/O pins can drive 24 PWM channels directly with hardware debounce and dead-time insertion. The instant-on flash-based configuration means the lighting show restarts within milliseconds after power-cycle, with no waiting for FPGA bitstream loads. The industrial temperature rating handles outdoor LED facade deployments. Recommended for: stage lighting, architectural LEDs, signage controllers.
Recommended
Motor Control Peripheral Interface
The EPM240T100I3N is used in brushless-DC and stepper motor-control boards to generate quadrature encoder interfaces (QEI), Hall-sensor decoders, and PWM-with-dead-time controllers for the gate-driver front end. The 4.6 ns tPD1 propagation delay combined with MultiVolt I/O lets the CPLD interface directly to 1.8 V FPGA controllers and 3.3 V Hall sensors on the same board. The 4 global clock networks can be routed to independent PWM channels, simplifying timing closure on 6-step commutation tables. The 8 Kbit user flash stores motor calibration tables and serial numbers. Recommended for: drones, robotic actuators, CNC machines, e-bike controllers.
Recommended
Test and Measurement Instrument Front-Ends
Test-equipment manufacturers embed the EPM240T100I3N as a glue-logic hub in bench oscilloscopes, logic analyzers, and protocol analyzers where deterministic pin-to-pin timing is mandatory. The 80 I/O pins can be user-configured into 4 independent test pods (16 channels each), each generating programmable stimulus patterns with sub-5 ns skew. The JTAG/ISP interface allows field upgrades of test vectors without disassembling the unit. The industrial -40C to +100C range meets lab and field-test thermal requirements. The 8 Kbit flash stores customer license keys and instrument calibration data, eliminating external EEPROM. Recommended for: oscilloscopes, protocol analyzers, production-line ICT fixtures.
Recommended
Recommended Products Summary
Engineering reference data for EPM240T100I3N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240T100C5N | EPM240T100C4N | EPM240T100C3N | EPM240T100A5N | EPM240GT100I5N | EPM570T100C5N |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 (T100) | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same |
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Macrocell Count | 192 | 192 (same die) | 192 (same die) | 192 (same die) | 192 (same die) | 240 (enhanced) | 570 (3x logic capacity) |
| Maximum User I/O | 80 | 80 | 80 | 80 | 80 | 80 | 76 (4 pins reserved) |
| Temperature Grade | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Automotive | Industrial (-40C to +100C) | Commercial (0C to +85C) |
| Speed Grade | 3 | 5 (faster) | 4 | 3 (same) | 5 (faster) | 5 | 5 |
| On-chip User Flash | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Supply Voltage (Core) | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V |
| Pin-to-pin Logic Delay (tPD1) | 4.6 ns (speed grade 3) | 3.5 ns (speed grade 5) | 4.0 ns (speed grade 4) | 4.6 ns (speed grade 3) | 3.5 ns (speed grade 5) | 3.5 ns (speed grade 5) | 3.5 ns (speed grade 5) |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Industrial temperature grade at speed grade 3 (vs EPM240T100C5N)
- Same TQFP-100 footprint with 240 macrocells (vs EPM240GT100I5N)
- 8 Kbit on-chip user flash eliminates external EEPROM (vs Discrete EEPROM + 74-series glue logic)
- 3x logic capacity with same package footprint (vs EPM570T100C5N)
Design Notes
Place all VCCINT and VCCIO decoupling capacitors within 2 mm of their respective pins. Use 0.1 uF X7R ceramic capacitors on each VCCIO bank pin and 10 uF bulk tantalum or polymer capacitors on each VCCINT pin. The TQFP-100 package has 4 GND pins (1, 12, 23, 32, 43, 53, 64, 73, 84 area) - tie all to a low-impedance ground plane with multiple vias to reduce ground bounce on JTAG transitions. Estimated: junction temperature rise is negligible (<5C) at typical 100 MHz operation given the 0.18 um flash process low static current.
Configure JTAG chain ordering so the EPM240T100I3N is upstream of any downstream FPGA or configuration device. Use a 4.7 kohm pull-up on TCK and a 4.7 kohm pull-up on TMS to keep the JTAG state machine in Test-Logic-Reset during power-up. If the board is deployed in noisy industrial environments, add a 33 ohm series damping resistor on TCK to suppress ringing below 100 MHz. MultiVolt I/O banks should not be mixed-voltage during in-system programming - hold all banks at 3.3 V during JTAG ISP for reliable configuration.
Do not confuse the EPM240T100I3N (industrial, speed grade 3) with the EPM240T100C5N (commercial, speed grade 5). The 'I' suffix indicates industrial temperature grade and the '3' suffix indicates speed grade 3; commercial parts use 'C' and grades 3/4/5/8. Mixing the two part numbers in a BOM for an industrial-rated board will fail at low temperature or high junction temperature. Note that the EPM570T100C5N shares the TQFP-100 footprint but pins 37 and 90 must be tied to GND and pins 39 and 88 to 3.3V - leaving them as I/O (like EPM240) will prevent the EPM570 from configuring. Reference: Altera MAX II vertical migration AN-422.
Allocate the four global clock networks (CLK0-CLK3) only to high-fanout clock inputs to preserve timing margins. Avoid routing general-purpose logic through the dedicated clock pins - they have special input buffers optimized for low-jitter clocks. For designs with multiple clock domains, place the CPLD within 50 mm of the clock source and use matched-length traces on differential clock pairs. The exposed thermal pad on TQFP-100 (if present on the package variant) should be soldered to a thermal copper pour to improve heat dissipation in high-utilization designs exceeding 80% macrocell usage.
Compliance Information
RoHS compliant per the manufacturer ordering information. The EPM240T100I3N is not AEC-Q100 qualified; for automotive applications choose the EPM240T100A5N (automotive grade). REACH SVHC status to be confirmed by the latest manufacturer Material Declaration.
