EPM240T100I5 vs EPM240T100I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100I5 sa pamamagitan ng Intel at EPM240T100I3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM240T100I5 | EPM240T100I3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | MAX II | MAX II |
| Series | EPM240 | — |
| Device Sub-family | EPM240T100 | — |
| Logic Elements (LE) | 240 | — |
| Equivalent Macrocells | 192 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Maximum User I/O Pins | 80 | 80 |
| Packhaging | TQFP-100 (100-pin) | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Temperature na Operasyon | -40C to +100C (industrial) | — |
| Speed Grade | I5 | 3 |
| Core Voltage | 3.3 V | — |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Propagation Delay (typical) | 4-7 ns | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG / IEEE 1149.1 ISP |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant |
| Device Logic Elements / Macrocells | — | 192 macrocells |
| Number of Logic Array Blocks (LABs) | — | 4 |
| On-chip User Flash Memory | — | 8 Kbits |
| Internal Performance | — | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | — | 4.6 ns |
| Global Clock Networks | — | 4 |
| Technology Node | — | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| Temperature ng Junction na Operasyon | — | -40C to +100C (industrial, 'I' grade) |
| Instant-on (non-volatile) | — | Yes (flash-based) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |