EPM5064JC vs EPM5032JC25 比較
詳細並排比較 EPM5064JC 由 Altera 與 EPM5032JC25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC | EPM5032JC25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | — |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| 封裝 | 68-pin PLCC (JEDEC) | 28-pin PLCC (JC) |
| 安裝類型 | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | — |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Device | — | EPM5032 |
| Logic Elements | — | 32 macrocells |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Internal Frequency | — | 62.5 MHz |
| Product Terms | — | 320 |
| Flip-Flops | — | 32 |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs to Array | — | 24 |
| 輸出數量 | — | 16 |
| Architecture | — | PAL-type macrocells with global Programmable Interconnect Array (PIA) |
| Technology | — | CMOS EPROM, UV-erasable (windowed) / OTP |
| 供應電壓 | — | 5 V (TTL-level I/O) |