EPM5064LI vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064LI sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064LI EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable PLD)
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Number of Terminals 44 —
Package Code QCCJ (PLCC-44, J-bend) —
Package Shape Square —
Configuration Memory UV-Erasable / OTP (EPROM-based) EPROM (UV-erasable window or OTP)
Supply Voltage (VCC) 4.5 V to 5.5 V 5 V (typical, 4.75 V - 5.25 V range)
Operating Temperature Grade Industrial —
Maksimum na Taktiko ng Oras 33.3 MHz —
Propagation Delay (tPD) 55 ns (typical) —
I/O Pins 28 bidirectional —
Dedicated Inputs 7 —
Total User Inputs 36 —
Process Technology 1-micron EPIC CMOS —
Latch-up Immunity 500 mA typical at 125 C —
Uri ng Pagpapasok Surface Mount Surface Mount (socketed)
Tindminan RoHS [DATA_NEEDED: confirm RoHS status - legacy Altera part] [DATA_NEEDED: RoHS compliance]
Usable Gates — 1,250 (approx.)
Logic Array Inputs — 36
Logic Array Outputs — 64
Packhaging — 68-pin PLCC (JEDEC)
I/O Logic Level — TTL / CMOS compatible
Temperature na Operasyon — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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