EPM5128LC2 vs EPM5128JC Comparison
Detailed side-by-side comparison of EPM5128LC2 by Altera and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128LC2 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD / CPLD |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | 35 ns |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Configuration Memory | On-chip EPROM (non-volatile) | UV-erasable EPROM (windowed package) |
| Boundary Scan | JTAG / IEEE 1149.1 | JTAG IEEE 1149.1 (family feature) |
| Operating Temperature | -40 C to +85 C (extended commercial) | Commercial 0C to +70C |
| Package | PGA (Pin Grid Array, ceramic) | — |
| Mounting Type | Through-Hole / Socketed | Surface Mount (PLCC socket or solder) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - legacy part] |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Number of Pins | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |