EPM5192LC-35 vs EPM5192LC-2N 比較
詳細並排比較 EPM5192LC-35 由 Altera 與 EPM5192LC-2N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-35 | EPM5192LC-2N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | -2 (tPD approximately 25 ns) |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | LC (ceramic J-leaded, windowed UV-erasable package family) |
| 安裝類型 | Surface Mount | Surface Mount (LC package) |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| 工作溫度 | Commercial (0C to +70C) per LC suffix | Commercial (0C to +70C) - inferred from speed-grade -2 designation |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | Programmable Logic Array (PLA) with global PIA |
| I/O Standard | TTL | — |
| RoHS 狀態 | Non-compliant (ceramic hermetic package) | Compliant (per -N lead-free suffix) |
| 生命週期狀態 | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Macrocells | — | 192 |
| Flip-Flops | — | 192 |
| Logic Elements | — | 192 macrocells (PAL/GAL-style AND-OR array) |
| Propagation Delay (typical) | — | 25 ns |
| 供應電壓 | — | 5 V (typical) |
| Programmability | — | UV-erasable EPROM cell |
| Lead-Free | — | Yes (per -N suffix) |
| Programming Interface | — | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) |