EPM7128SQC100-7 vs EPM7128SQC100-15 比較
詳細並排比較 EPM7128SQC100-7 由 Intel 與 EPM7128SQC100-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 Obsolete
規格比較
| 參數 | EPM7128SQC100-7 | EPM7128SQC100-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| 單價 (USD) | — | $8.20 |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Family | MAX 7000S | MAX 7000 |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS, EEPROM-based, non-volatile | — |
| 封裝 | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Non-RoHS (legacy SnPb package) | Non-compliant (SnPb lead finish - legacy PQFP) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Supply Voltage (VCCINT) | — | 5 V (5% tolerance) |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| MSL 等級 | — | 3 (168 hours) |