EPM9400RC208-20 vs EPM9320RC208-20 Comparison

Detailed side-by-side comparison of EPM9400RC208-20 by Altera and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9400RC208-20 EPM9320RC208-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $60.49 $21.90
Family MAX 9000 MAX 9000
Programmable Type In System Programmable (ISP) β€”
Macro Cells 400 β€”
Usable Gates 8,000 6,000
Pin-to-Pin Propagation Delay 20 ns β€”
Maximum Operating Frequency 100 MHz β€”
Supply Voltage (Internal) 4.75 V to 5.25 V β€”
Configuration Technology EEPROM-based (non-volatile) β€”
JTAG Interface IEEE Std. 1149.1 β€”
Package 208-pin RQFP (28x28 mm) 208-RQFP, exposed pad (208-BFQFP)
Supplier Device Package 208-RQFP β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] 0 Β°C to 70 Β°C (commercial)
Number of I/O Pins [DATA_NEEDED: user I/O count] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
MSL Level [DATA_NEEDED: moisture sensitivity level] β€”
Speed Grade -20 (20 ns) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 320
Logic Array Blocks (LABs) β€” 20
Maximum I/O Pins β€” 132
Propagation Delay (tPD max) β€” 20 ns
Supply Voltage (VCCINT) β€” 4.75 V to 5.25 V
Programming Technology β€” EEPROM, in-system programmable (ISP)
Boundary-Scan Interface β€” IEEE Std. 1149.1 (JTAG)
Architecture β€” Multiple Array Matrix (MAX), 3rd generation
Process Technology β€” CMOS, 5.0 V EEPROM
Reprogrammability β€” Yes, unlimited ISP cycles

Datasheets & Resources

Browse All Products Create BOM Request Quote