EP910JM-40 vs EP910DC-35 Vergleich

Detaillierter Direktvergleich von EP910JM-40 von Altera und EP910DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910JM-40 EP910DC-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,95 $10,95
Device Family Altera Classic EPLD —
Series EP910 —
Logic Type EPLD (UV-Erasable PAL-type) —
Macrocells 24 24
Dedicated Inputs 12 12
I/O Lines 24 —
Total Inputs (max) 36 —
Total Outputs (max) 24 —
Product Terms 240 240
External Clock Inputs 2 —
Propagation Delay (tPD) 40 ns —
Process Technology CMOS —
Gehäuse JLCC-28 (windowed ceramic, J-lead) 40-pin CDIP (Ceramic DIP) with quartz window
Montageart Surface Mount —
RoHS-Status [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Method UV erase + EPROM programmer JEDEC fuse map via device programmer; UV erase
Betriebstemperatur 0C to +70C (commercial) [DATA_NEEDED: confirm grade] 0 °C to +70 °C (commercial)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Family — Classic EPLD EP910
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maximale Taktfrequenz — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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