EP910JM-40 vs EP910DC-35 비교
다음의 상세 나란히 비교: EP910JM-40 제조: Altera 및 EP910DC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910JM-40 | EP910DC-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $10.95 |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | 240 |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS | — |
| 패키지 | JLCC-28 (windowed ceramic, J-lead) | 40-pin CDIP (Ceramic DIP) with quartz window |
| 실장 유형 | Surface Mount | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Programming Method | UV erase + EPROM programmer | JEDEC fuse map via device programmer; UV erase |
| 동작 온도 | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | 0 °C to +70 °C (commercial) |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| 최대 클록 주파수 | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |