EP910JM-40 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910JM-40 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910JM-40 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Altera Classic EPLD —
Series EP910 —
Logic Type EPLD (UV-Erasable PAL-type) —
Macrocells 24 24
Dedicated Inputs 12 12
I/O Lines 24 —
Total Inputs (max) 36 —
Total Outputs (max) 24 —
Product Terms 240 240
External Clock Inputs 2 —
Propagation Delay (tPD) 40 ns —
Process Technology CMOS —
Packhaging JLCC-28 (windowed ceramic, J-lead) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Method UV erase + EPROM programmer JEDEC fuse map via device programmer; UV erase
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: confirm grade] 0 °C to +70 °C (commercial)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Family — Classic EPLD EP910
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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