EP910JM-40 vs EP910DC-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910JM-40 disebabkan oleh Altera dan EP910DC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910JM-40 | EP910DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Logic Type | EPLD (UV-Erasable PAL-type) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Product Terms | 240 | 240 |
| External Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS | — |
| Kemasan | JLCC-28 (windowed ceramic, J-lead) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: RoHS status - UV-windowed ceramic package typically not RoHS compliant] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Programming Method | UV erase + EPROM programmer | JEDEC fuse map via device programmer; UV erase |
| Suhu Operasi | 0C to +70C (commercial) [DATA_NEEDED: confirm grade] | 0 °C to +70 °C (commercial) |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Frekuensi Klock Maksimum | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |